MC74VHC139_11 Datasheet, PDF (1/8 Pages) ON Semiconductor – Dual 2-to-4 Decoder/ Demultiplexer

MC74VHC139
Dual 2-to-4 Decoder/
Demultiplexer
The MC74VHC139 is an advanced high speed CMOS 2−to−4
decoder/ demultiplexer fabricated with silicon gate CMOS
technology. It achieves high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining CMOS low power
dissipation.
When the device is enabled (E = low), it can be used for gating or as
a data input for demultiplexing operations. When the enable input is
held high, all four outputs are fixed high, independent of other inputs.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7 V, allowing the interface of 5 V
systems to 3 V systems.
• High Speed: t_PD = 5.0 ns (Typ) at V_CC = 5 V
• Low Power Dissipation: I_CC = 4 mA (Max) at T_A = 25°C
• High Noise Immunity: V_NIH = V_NIL = 28% V_CC
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2 V to 5.5 V Operating Range
• Low Noise: V_OLP = 0.8 V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
• ESD Performance: Human Body Model > 2000 V;
Machine Model > 200 V
• Chip Complexity: 100 FETs or 25 Equivalent Gates
• These Devices are Pb−Free and are RoHS Compliant
http://onsemi.com
SOIC−16
D SUFFIX
CASE 751B
MARKING DIAGRAMS
16
9
VHC139
AWLYYWW
1
8
16
9
TSSOP−16
DT SUFFIX
CASE 948F
VHC
139
ALYW
1
8
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
PIN ASSIGNMENT
Ea 1
A0a ²
16 _VCC
15 _Eb
A1a ³
Y0a ⁴
Y1a 5
Y2a 6
Y3a 7
GND 8
14 _A0b
13 _A1b
12 Y0b
11 _Y1b
10 Y2b
9 Y3b
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
© Semiconductor Components Industries, LLC, 2011
1
May, 2011 − Rev. 4
Publication Order Number:
MC74VHC139/D