MC74VHC138DG Datasheet, PDF (1/8 Pages) ON Semiconductor – 3-to-8 Line Decoder

MC74VHC138
3-to-8 Line Decoder
The MC74VHC138 is an advanced high speed CMOS 3−to−8
decoder fabricated with silicon gate CMOS technology. It achieves
high speed operation similar to equivalent Bipolar Schottky TTL
while maintaining CMOS low power dissipation.
When the device is enabled, three Binary Select inputs (A0 − A2)
determine which one of the outputs (Y0 − Y7) will go Low. When
enable input E3 is held Low or either E2 or E1 is held High, decoding
function is inhibited and all outputs go high. E3, E2, and E1 inputs are
provided to ease cascade connection and for use as an address decoder
for memory systems.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7V, allowing the interface of 5V systems
to 3V systems.
• High Speed: t_PD = 5.7ns (Typ) at V_CC = 5 V
• Low Power Dissipation: I_CC = 4 μA (Max) at T_A = 25°C
• High Noise Immunity: V_NIH = V_NIL = 28% V_CC
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2 V to 5.5 V Operating Range
• Low Noise: V_OLP = 0.8 V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
• ESD Performance: HBM > 2000 V; Machine Model > 200 V
• Chip Complexity: 122 FETs or 30.5 Equivalent Gates
• These Devices are Pb−Free and are RoHS Compliant
http://onsemi.com
MARKING DIAGRAMS
SOIC−16
D SUFFIX
CASE 751B
16
9
VHC138G
AWLYWW
1
8
16
9
TSSOP−16
DT SUFFIX
CASE 948F
VHC
138
ALYW G
G
1
8
VHC138 = Specific Device Code
A
= Assembly Location
WL, L = Wafer Lot
Y
= Year
WW, W = Work Week
G or G = Pb−Free Package
ORDERING INFORMATION
Device
Package Shipping
MC74VHC138DG
SOIC−16 48 Units/Rail
MC74VHC138DR2G SOIC−16 2500 Units/Reel
MC74VHC138DTR2G TSSOP−16 2500 Units/Reel
© Semiconductor Components Industries, LLC, 2011
1
May, 2011 − Rev. 5
Publication Order Number:
MC74VHC138/D