MC74LVX4053DTR2G Datasheet, PDF (1/15 Pages) ON Semiconductor – Analog Multiplexer Demultiplexer

MC74LVX4053
Analog Multiplexer/
Demultiplexer
High−Performance Silicon−Gate CMOS
The MC74LVX4053 utilizes silicon−gate CMOS technology to
achieve fast propagation delays, low ON resistances, and low OFF
leakage currents. This analog multiplexer/demultiplexer controls
analog voltages that may vary across the complete power supply range
(from V_CC to V_EE).
The LVX4053 is similar in pinout to the LVX8053, the HC4053A,
and the metal−gate MC14053B. The Channel−Select inputs determine
which one of the Analog Inputs/Outputs is to be connected, by means
of an analog switch, to the Common Output/Input. When the Enable
pin is HIGH, all analog switches are turned off.
The Channel−Select and Enable inputs are compatible with standard
CMOS outputs; with pullup resistors, they are compatible with
LSTTL outputs.
This device has been designed so the ON resistance (R_ON) is more
linear over input voltage than the R_ON of metal−gate CMOS analog
switches and High−Speed CMOS analog switches.
Features
• Fast Switching and Propagation Speeds
• Low Crosstalk Between Switches
• Analog Power Supply Range (V_CC − V_EE) = *3.0 V to )3.0 V
• Digital (Control) Power Supply Range (V_CC − GND) = 2.5 to 6.0 V
• Improved Linearity and Lower ON Resistance Than Metal−Gate,
HSL, or VHC Counterparts
• Low Noise
• Designed to Operate on a Single Supply with V_EE = GND, or Using
Split Supplies up to ±3.0 V
• Break−Before−Make Circuitry
• These Devices are Pb−Free and are RoHS Compliant
http://onsemi.com
MARKING
DIAGRAMS
SOIC−16
D SUFFIX
CASE 751B
16
LVX4053G
AWLYWW
1
16
TSSOP−16
DT SUFFIX
CASE 948F
LVX
4053
ALYWG
G
1
SOEIAJ−16
M SUFFIX
CASE 966
16
LVX4053
ALYWG
1
LVX4053 = Specific Device Code
A
= Assembly Location
WL, L = Wafer Lot
Y
= Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
V_CC Y X X1 X0 A B C
16 15 14 13 12 11 10 9
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
12345678
Y1 Y0 Z1 Z Z0 Enable V_EE GND
Figure 1. Pin Connection and Marking Diagram
(Top View)
© Semiconductor Components Industries, LLC, 2011
1
May, 2011 − Rev. 8
Publication Order Number:
MC74LVX4053/D