MC74LCX373 Datasheet, PDF (1/8 Pages) Motorola, Inc – LOW-VOLTAGE CMOS OCTAL TRANSPARENT LATCH

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Low-Voltage CMOS Octal
Transparent Latch
With 5V-Tolerant Inputs and Outputs
(3-State, Non-Inverting)
The MC74LCX373 is a high performance, non–inverting octal
transparent latch operating from a 2.7 to 3.6V supply. High impedance
TTL compatible inputs significantly reduce current loading to input drivers
while TTL compatible outputs offer improved switching noise
performance. A VI specification of 5.5V allows MC74LCX373 inputs to be
safely driven from 5V devices.
The MC74LCX373 contains 8 D–type latches with 3–state outputs.
When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters
the latches. In this condition, the latches are transparent, i.e., a latch
output will change state each time its D input changes. When LE is LOW,
the latches store the information that was present on the D inputs a setup
time preceding the HIGH–to–LOW transition of LE. The 3–state standard
outputs are controlled by the Output Enable (OE) input. When OE is
LOW, the standard outputs are enabled. When OE is HIGH, the standard
outputs are in the high impedance state, but this does not interfere with
new data entering into the latches.
• Designed for 2.7 to 3.6V VCC Operation
• 5V Tolerant — Interface Capability With 5V TTL Logic
• Supports Live Insertion and Withdrawal
• IOFF Specification Guarantees High Impedance When VCC = 0V
• LVTTL Compatible
• LVCMOS Compatible
• 24mA Balanced Output Sink and Source Capability
• Near Zero Static Supply Current in All Three Logic States (10µA)
Substantially Reduces System Power Requirements
• Latchup Performance Exceeds 500mA
• ESD Performance: Human Body Model >2000V; Machine Model >200V
MC74LCX373
LOW–VOLTAGE
CMOS OCTAL
TRANSPARENT LATCH
20
1
20
1
20
1
20
1
DW SUFFIX
PLASTIC SOIC
CASE 751D–04
M SUFFIX
PLASTIC SOIC EIAJ
CASE 967–01
SD SUFFIX
PLASTIC SSOP
CASE 940C–03
DT SUFFIX
PLASTIC TSSOP
CASE 948E–02
Pinout: 20–Lead (Top View)
VCC O7 D7 D6 O6 O5 D5 D4 O4 LE
20 19 18 17 16 15 14 13 12 11
PIN NAMES
Pins
Function
OE
LE
D0–D7
O0–O7
Output Enable Input
Latch Enable Input
Data Inputs
3–State Latch Outputs
1 2 3 4 5 6 7 8 9 10
OE O0 D0 D1 O1 O2 D2 D3 O3 GND
11/96
© Motorola, Inc. 1996
1
REV 4