MC74HCT74A Datasheet, PDF (1/8 Pages) Motorola, Inc – Dual D Flip-Flop with Set and Reset with LSTTL Compatible Inputs

MC74HCT74A
Dual D Flip-Flop with Set
and Reset with LSTTL
Compatible Inputs
High–Performance Silicon–Gate CMOS
The MC74HCT74A is identical in pinout to the LS74. This device
may be used as a level converter for interfacing TTL or NMOS outputs
to High Speed CMOS inputs.
This device consists of two D flip–flops with individual Set, Reset,
and Clock inputs. Information at a D–input is transferred to the
corresponding Q output on the next positive going edge of the clock
input. Both Q and Q outputs are available from each flip–flop. The Set
and Reset inputs are asynchronous.
• Output Drive Capability: 10 LSTTL Loads
• TTL NMOS Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 µA
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 136 FETs or 34 Equivalent Gates
LOGIC DIAGRAM
RESET 1 ¹
DATA 1 ²
3
CLOCK 1
5
Q1
6
Q1
SET 1 ⁴
13
RESET 2
PIN 14 = VCC
PIN 7 = GND
DATA 2 ¹²
11
CLOCK 2
9
Q2
8
Q2
10
SET 2
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Design Criteria
Value
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Internal Gate Count*}
34
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Internal Gate Propagation Delay}
1.5
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Internal Gate Power Dissipation}
5.0
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Speed Power Product
.0075
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ *Equivalent to a two–input NAND gate.
Units
ea.
ns
µW
pJ
© Semiconductor Components Industries, LLC, 2000
1
March, 2000 – Rev. 8
http://onsemi.com
PDIP–14
N SUFFIX
CASE 646
MARKING
DIAGRAMS
14
MC74HCT74AN
AWLYYWW
SOIC–14
D SUFFIX
CASE 751A
1
14
HCT74A
AWLYWW
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
PIN ASSIGNMENT
RESET 1 1
DATA 1 2
CLOCK 1 3
SET 1 4
Q1 5
Q1 6
GND 7
14 VCC
13 RESET 2
12 DATA 2
11 CLOCK 2
10 SET 2
9 Q2
8 Q2
FUNCTION TABLE
Inputs
Set Reset Clock Data
LH
HL
LL
HH
HH
HH
HH
HH
XX
XX
XX
H
L
LX
HX
X
Outputs
QQ
HL
LH
H* H*
HL
LH
No Change
No Change
No Change
*Both outputs will remain high as long as Set and
Reset are low, but the output states are unpredict-
able if Set and Reset go high simultaneously.
ORDERING INFORMATION
Device
Package Shipping
MC74HCT74AN
PDIP–14 2000 / Box
MC74HCT74AD
SOIC–14
55 / Rail
MC74HCT74ADR2
SOIC–14 2500 / Reel
Publication Order Number:
MC74HCT74A/D