MC74HCT138A Datasheet, PDF (1/6 Pages) Motorola, Inc – 1-of-8 Decoder/Demultiplexer with LSTTL Compatible Inputs

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
1-of-8 Decoder/Demultiplexer
with LSTTL Compatible Inputs
MC74HCT138A
High–Performance Silicon–Gate CMOS
The MC74HCT138A is identical in pinout to the LS138. The HCT138A
may be used as a level converter for interfacing TTL or NMOS outputs to
High Speed CMOS inputs.
The HCT138A decodes a three–bit Address to one–of–eight active–lot
outputs. This device features three Chip Select inputs, two active–low and
one active–high to facilitate the demultiplexing, cascading, and chip–select-
ing functions. The demultiplexing function is accomplished by using the
Address inputs to select the desired device output; one of the Chip Selects is
used as a data input while the other Chip Selects are held in their active
states.
16
1
16
1
16
1
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
D SUFFIX
SOIC PACKAGE
CASE 751B–05
DT SUFFIX
TSSOP PACKAGE
CASE 948F–01
• Output Drive Capability: 10 LSTTL Loads
• TTL/NMOS Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 µA
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 122 FETs or 30.5 Equivalent Gates
ORDERING INFORMATION
MC74HCTXXXAN
MC74HCTXXXAD
MC74HCTXXXADT
Plastic
SOIC
TSSOP
PIN ASSIGNMENT
LOGIC DIAGRAM
A0 1
A1 2
16 VCC
15 Y0
ADDRESS
INPUTS
A0 ¹
A1 ²
A2 ³
15 _Y0
14 _Y1
13 _Y2
12 _Y3
11 _Y4
10
Y5
9 _Y6
7
Y7
ACTIVE–LOW
OUTPUTS
A2 3
CS2 4
CS3 5
CS1 6
Y7 7
GND 8
14 _Y1
13 Y2
12 Y3
11 Y4
10 Y5
9 Y6
FUNCTION TABLE
CHIP–
CS1 ⁶
SELECT _CS2 ⁴
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _INPUTS
CS3
5
PIN 16 = VCC
PIN 8 = GND
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Design Criteria}
Value
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Internal Gate Count*}
30.5
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Internal Gate Propagation Delay}
1.5
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Internal Gate Power Dissipation}
5.0
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Speed Power Product}
.0075
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{*Equivalent to a two–input NAND gate.}
Units
ea.
ns
µW
pJ
Inputs
Outputs
CS1CS2 CS3 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
X X H XXX HHH HHHH H
X H X XXX HHH HHHH H
L X X XXX HHH HHHH H
H L L LLL LHHHHHHH
H L L LLHH L HHHHHH
H L L LHL HH L HHHHH
H L L LHH H H H L H H H H
H L L HLL HHHH L HHH
H L L HLHHHHHH L HH
H L L HHL H H H H H H L H
H L L HHH H H H H H H H L
H = high level (steady state)
L = low level (steady state)
X = don’t care
10/95
© Motorola, Inc. 1995
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