MC74HCT125A Datasheet, PDF (1/8 Pages) ON Semiconductor – Quad 3-State Noninverting Buffer with LSTTL Compatible Inputs

MC74HCT125A
Quad 3-State Noninverting
Buffer with LSTTL
Compatible Inputs
High−Performance Silicon−Gate CMOS
The MC74HCT125A is identical in pinout to the LS125. The device
inputs are compatible with standard CMOS and LSTTL outputs.
The MC74HCT125A noninverting buffer is designed to be used
with 3−state memory address drivers, clock drivers, and other
bus−oriented systems. The devices have four separate output enables
that are active−low.
Features
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 mA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the JEDEC Standard No. 7A Requirements
• Chip Complexity: 72 FETs or 18 Equivalent Gates
• These are Pb−Free Devices
PIN ASSIGNMENT
OE1 1
A1 2
Y1 3
OE2 4
A2 5
Y2 6
GND 7
14 V_CC
13 OE4
12 A4
11 Y4
10 OE3
9 A3
8 Y3
FUNCTION TABLE
HCT125A
Inputs Output
A OE Y
HL
H
LL
L
XH
Z
LOGIC DIAGRAM
Active−Low Output Enables
A1
2
3
Y1
OE1
1
5
A2
6
Y2
OE2
4
9
A3
8 _Y3
OE3
10
12
A4
13
OE4
PIN 14 = V_CC
PIN 7 = GND
11
Y4
14
1
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MARKING
DIAGRAMS
14
PDIP−14
N SUFFIX
CASE 646
MC74HCT125AN
AWLYYWWG
1
14
1
14
SOIC−14
D SUFFIX
CASE 751A
1
HCT125AG
AWLYWW
14
1
TSSOP−14
DT SUFFIX
CASE 948G
14
HCT
125A
ALYWG
G
1
14
14
1
SOEIAJ−14
F SUFFIX
CASE 965
74HCT125A
ALYWG
1
A
=
Assembly Location
L, WL =
Wafer Lot
Y, YY =
Year
W, WW =
Work Week
G
= Pb−Free Package
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
© Semiconductor Components Industries, LLC, 2009
1
November, 2009 − Rev. 1
Publication Order Number:
MC74HCT125A/D