MC74HC175A_05 Datasheet, PDF (1/10 Pages) ON Semiconductor – Quad D Flip−Flop with Common Clock and Reset High−Performance Silicon−Gate CMOS

MC74HC175A
Quad D Flip−Flop with
Common Clock and Reset
High−Performance Silicon−Gate CMOS
The MC74HC175A is identical in pinout to the LS175. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device consists of four D flip−flops with common Reset and
Clock inputs, and separate D inputs. Reset (active−low) is
asynchronous and occurs when a low level is applied to the Reset
input. Information at a D input is transferred to the corresponding Q
output on the next positive going edge of the Clock input.
Features
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1 mA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity 166 FETs or 41.5 Equivalent Gates
• Pb−Free Packages are Available*
16
1
http://onsemi.com
MARKING
DIAGRAMS
16
PDIP−16
N SUFFIX
CASE 648
MC74HC175AN
AWLYYWW
1
16
1
16
1
16
SOIC−16
D SUFFIX
CASE 751B
HC175AG
AWLYWW
1
TSSOP−16
DT SUFFIX
CASE 948F
16
HC
175A
ALYWG
G
1
16
1
SOEIAJ−16
F SUFFIX
CASE 966
16
74HC175A
ALYWG
1
A
= Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
G
= Pb−Free Package
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2005
1
June, 2005 − Rev. 3
Publication Order Number:
MC74HC175A/D