MC74HC175A Datasheet, PDF (1/8 Pages) ON Semiconductor – Quad D Flip-Flop with Common Clock and Reset

MC74HC175A
Quad D Flip-Flop with
Common Clock and Reset
High–Performance Silicon–Gate CMOS
The MC74HC175A is identical in pinout to the LS175. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device consists of four D flip–flops with common Reset and
Clock inputs, and separate D inputs. Reset (active–low) is
asynchronous and occurs when a low level is applied to the Reset
input. Information at a D input is transferred to the corresponding Q
output on the next positive going edge of the Clock input.
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity 166 FETs or 41.5 Equivalent Gates
LOGIC DIAGRAM
CLOCK ⁹
DATA
INPUTS
D0 ⁴
D1 ⁵
D2 ¹²
D3 ¹³
RESET ¹
PIN 16 = VCC
PIN 8 = GND
2 _Q0
3 _Q0
7 _Q1
6 _Q1
10 _Q2
11 _Q2
15 _Q3
14 _Q3
INVERTING
AND
NONINVERTING
OUTPUTS
FUNCTION TABLE
Inputs
Reset Clock D
L
XX
H
H
H
L
H
LX
Outputs
QQ
LH
HL
LH
No Change
http://onsemi.com
16
1
16
1
PDIP–16
N SUFFIX
CASE 648
SO–16
D SUFFIX
CASE 751B
MARKING
DIAGRAMS
16
MC74HC175AN
AWLYYWW
1
16
HC175A
AWLYWW
1
16
16
1
TSSOP–16
DT SUFFIX
CASE 948F
HC
175A
ALYW
1
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
PIN ASSIGNMENT
RESET 1
Q0 2
Q0 3
D0 4
D1 5
Q1 6
Q1 7
GND 8
16 VCC
15 Q3
14 Q3
13 D3
12 D2
11 Q2
10 Q2
9 CLOCK
ORDERING INFORMATION
Device
Package Shipping
MC74HC175AN
PDIP–16 2000 / Box
MC74HC175AD
SOIC–16 48 / Rail
MC74HC175ADR2
SOIC–16 2500 / Reel
MC74HC175ADT
TSSOP–16 96 / Rail
MC74HC175ADTR2 TSSOP–16 2500 / Reel
© Semiconductor Components Industries, LLC, 1999
1
March, 2000 – Rev. 2
Publication Order Number:
MC74HC175A/D