MC14598B_06 Datasheet, PDF (1/6 Pages) ON Semiconductor – 8−Bit Bus−Compatible Latches

MC14598B
8−Bit Bus−Compatible
Latches
The MC14598B is an 8−bit latch addressed with an external binary
address. The 8 latch−outputs are high drive, three−state and bus line
compatible. The drive capability allows direct applications with MPU
systems such as the Motorola 6800 family.
The latches of the MC14598B are accessed via the Address pins,
A0, A1, and A2.
All 8 outputs from the latches are available in parallel when Enable
is in the low state. Data is entered into a selected latch from the Data
pin when the Strobe is high. Master reset is available on both parts.
Features
• Serial Data Input
• Three−State Bus Compatible Parallel Outputs
• Three−State Control Pin (Enable) TTL Compatible Input
• Open Drain Full Flag (Multiple Latch Wire−O Ring)
• Master Reset
• Level Shifting Inputs on All Except Enable
• Diode Protection — All Inputs
• Supply Voltage Range — 3.0 Vdc to 18 Vdc
• Capable of Driving TTL Over Rated Temperature Range With
Fanout as Follows: 1 TTL Load
4 LSTTL Loads
• Pb−Free Package is Available*
MAXIMUM RATINGS (Voltages Referenced to V_SS)
Parameter
Symbol
Value
Unit
DC Supply Voltage Range
Input Voltage Range, enable
(DC or Transient)
V_DD −0.5 to +18.0 V
V_in
−0.5 to V_DD V
+0.5
Input Voltage Range, all Other Inputs
(DC or Transient)
V_in
−0.5 to V_DD V
+12
Output Voltage Range, (DC or Transient)
V_out
−0.5 to V_DD V
+0.5
Input or Output Current (DC or Transient) I_in, I_out
±10
mA
per Pin
Power Dissipation per Package (Note 1)
P_D
500
mW
Ambient Temperature Range
T_A
−55 to +125 °C
Storage Temperature Range
T_stg −65 to +150 °C
Lead Temperature (8−Second Soldering)
T_L
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/_C From
65_C To 125_C
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
1
June, 2006 − Rev. 6
http://onsemi.com
PDIP−18
P SUFFIX
CASE 707
1
MARKING DIAGRAM
18
MC14598BCP
AWLYYWWG
1
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
OUTPUT TRUTH TABLE
Enable
Outputs
1
High Impedance
0
D_n
D_n = State of nth latch
NC = NO CONNECTION
ORDERING INFORMATION
Device
Package
Shipping
MC14598BCP
PDIP−18 20 Units/Rail
MC14598BCPG
PDIP−18
(Pb−Free)
20 Units/Rail
This device contains protection circuitry to guard
against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum
rated voltages to this high−impedance circuit. For
proper operation, V_in and V_out should be constrained
to the range V_SS v (V_in or V_out) v V_DD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either V_SS or
V_DD). Unused outputs must be left open.
Publication Order Number:
MC14598B/D