MC14572UB_14 Datasheet, PDF (1/5 Pages) ON Semiconductor – Hex Gate

MC14572UB
Hex Gate
The MC14572UB hex functional gate is constructed with MOS
P−channel and N−channel enhancement mode devices in a single
monolithic structure. These complementary MOS logic gates find
primary use where low power dissipation and/or high noise immunity
is desired. The chip contains four inverters, one NOR gate and one
NAND gate.
Features
• Diode Protection on All Inputs
• Single Supply Operation
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• NOR Input Pin Adjacent to V_SS Pin to Simplify Use As An Inverter
• NAND Input Pin Adjacent to V_DD Pin to Simplify Use As An
Inverter
• NOR Output Pin Adjacent to Inverter Input Pin For OR Application
• NAND Output Pin Adjacent to Inverter Input Pin For AND
Application
• Capable of Driving Two Low−Power TTL Loads or One
Low−Power Schottky TTL Load over the Rated Temperature
Range
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable*
• This Device is Pb−Free and is RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to V_SS)
Parameter
Symbol
Value
Unit
DC Supply Voltage Range
V_DD −0.5 to +18.0 V
Input or Output Voltage Range
(DC or Transient)
V_in, V_out − 0.5 to V_DD V
+ 0.5
Input or Output Current (DC or Transient) I_in, I_out
±10
mA
per Pin
Power Dissipation, per Package (Note 1)
P_D
500
mW
Ambient Temperature Range
T_A
−55 to +125 °C
Storage Temperature Range
T_stg
−65 to +150 °C
Lead Temperature (8−Second Soldering)
T_L
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Package: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V_in and V_out should be constrained
to the range V_SS ≤ (V_in or V_out) ≤ V_DD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V_SS or V_DD). Unused outputs must be left open.
http://onsemi.com
1
SOIC−16
D SUFFIX
CASE 751B
PIN ASSIGNMENT
OUT_A 1
IN_A 2
OUT_B 3
IN_B 4
OUT_C 5
IN 1_C 6
IN 2_C 7
V_SS 8
16 V_DD
15 IN 2_F
14 IN 1_F
13 OUT_F
12 IN_E
11 OUT_E
10 IN_D
9 OUT_D
MARKING DIAGRAM
16
14572UG
AWLYWW
1
A
= Assembly Location
WL = Wafer Lot
YY
= Year
WW = Work Week
G
= Pb−Free Package
ORDERING INFORMATION
Device
Package
Shipping^†
MC14572UBDG
SOIC−16
(Pb−Free)
48 Units / Rail
MC14572UBDR2G SOIC−16 2500/Tape & Reel
(Pb−Free)
NLV14572UBDR2G* SOIC−16 2500/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2014
1
July, 2014 − Rev. 10
Publication Order Number:
MC14572UB/D