MC14569B_14 Datasheet, PDF (1/12 Pages) ON Semiconductor – Programmable Divide-By-N Dual 4-Bit Binary/BCD Down Counter

MC14569B
Programmable Divide-By-N
Dual 4-Bit Binary/BCD
Down Counter
The MC14569B is a programmable divide−by−N dual 4−bit binary
or BCD down counter constructed with MOS P−Channel and
N−Channel enhancement mode devices (complementary MOS) in
a monolithic structure.
This device has been designed for use with the MC14568B phase
comparator/counter in frequency synthesizers, phase−locked loops,
and other frequency division applications requiring low power
dissipation and/or high noise immunity.
Features
• Speed−up Circuitry for Zero Detection
• Each 4−Bit Counter Can Divide Independently in BCD or Binary Mode
• Can be Cascaded With MC14526B for Frequency Synthesizer
Applications
• All Outputs are Buffered
• Schmitt Triggered Clock Conditioning
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• This Device is Pb−Free and is RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to V_SS)
Symbol
Parameter
Value
Unit
V_DD
V_in, V_out
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
−0.5 to +18.0
V
−0.5 to V_DD + 0.5
V
I_in, I_out Input or Output Current
(DC or Transient) per Pin
±10
mA
P_D Power Dissipation, per Package
(Note 1)
500
mW
T_A
Ambient Temperature Range
T_stg Storage Temperature Range
T_L
Lead Temperature
(8−Second Soldering)
−55 to +125
°C
−65 to +150
°C
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Package: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V_in and V_out should be constrained
to the range V_SS ≤ (V_in or V_out) ≤ V_DD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V_SS or V_DD). Unused outputs must be left open.
http://onsemi.com
SOIC−16 WB
DW SUFFIX
CASE 751G
PIN ASSIGNMENT
ZERO
DETECT
1
CTL1 2
P0 3
P1 4
P2 5
P3 6
CASCADE
FEEDBACK
7
V_SS 8
16 V_DD
15 Q
14 P7
13 P6
12 P5
11 P4
10 CTL₂
9 CLOCK
MARKING DIAGRAM
16
14569B
AWLYYWWG
1
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
1
July, 2014 − Rev. 8
Publication Order Number:
MC14569B/D