MC14557B Datasheet, PDF (1/8 Pages) Motorola, Inc – 1-TO-64 BIT VARIABLE LENGTH SHIFT REGISTER

MC14557B
1-to-64 Bit Variable Length
Shift Register
The MC14557B is a static clocked serial shift register whose length
may be programmed to be any number of bits between 1 and 64. The
number of bits selected is equal to the sum of the subscripts of the
enabled Length Control inputs (L1, L2, L4, L8, L16, and L32) plus
one. Serial data may be selected from the A or B data inputs with the
A/B select input. This feature is useful for recirculation purposes. A
Clock Enable (CE) input is provided to allow gating of the clock or
negative edge clocking capability.
The device can be effectively used for variable digital delay lines or
simply to implement odd length shift registers.
• 1–64 Bit Programmable Length
• Q and Q Serial Buffered Outputs
• Asynchronous Master Reset
• All Inputs Buffered
• No Limit On Clock Rise and Fall Times
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low–power TTL Loads or one Low–power
Schottky TTL Load Over the Rated Temperature Range
MAXIMUM RATINGS (Voltages Referenced to V_SS) (Note 2.)
Symbol
Parameter
Value
Unit
V_DD
DC Supply Voltage Range
– 0.5 to +18.0
V
V_in, V_out Input or Output Voltage Range – 0.5 to V_DD + 0.5
V
(DC or Transient)
I_in, I_out
Input or Output Current
(DC or Transient) per Pin
±10
mA
P_D
Power Dissipation,
per Package (Note 3.)
500
mW
T_A
Ambient Temperature Range
T_stg
Storage Temperature Range
T_L
Lead Temperature
(8–Second Soldering)
– 55 to +125
°C
– 65 to +150
°C
260
°C
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
v v ^{high–impedance circuit. For proper operation, Vin and Vout should be constrained}
to the range V_SS (V_in or V_out) V_DD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V_SS or V_DD). Unused outputs must be left open.
http://onsemi.com
PDIP–16
P SUFFIX
CASE 648
MARKING
DIAGRAMS
16
MC14557BCP
AWLYYWW
1
16
SOIC–16
DW SUFFIX
CASE 751G
14557B
AWLYYWW
1
SOEIAJ–16
F SUFFIX
CASE 966
16
MC14557B
AWLYWW
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
ORDERING INFORMATION
Device
MC14557BCP
MC14557BDW
Package
PDIP–16
SOIC–16
Shipping
2000/Box
47/Rail
MC14557BDWR2 SOIC–16 1000/Tape & Reel
MC14557BF
SOEIAJ–16 See Note 1.
MC14557BFEL SOEIAJ–16 See Note 1.
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
© Semiconductor Components Industries, LLC, 2000
1
March, 2000 – Rev. 3
Publication Order Number:
MC14557B/D