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MC14555B Datasheet, PDF (1/8 Pages) Motorola, Inc – Dual Binary to 1-of-4 Decoder/Demultiplexer | |||
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MC14555B, MC14556B
Dual Binary to 1-of-4
Decoder/Demultiplexer
The MC14555B and MC14556B are constructed with
complementary MOS (CMOS) enhancement mode devices. Each
Decoder/Demultiplexer has two select inputs (A and B), an active low
Enable input (E), and four mutually exclusive outputs (Q0, Q1, Q2,
Q3). The MC14555B has the selected output go to the âhighâ state,
and the MC14556B has the selected output go to the âlowâ state.
Expanded decoding such as binaryâtoâhexadecimal (1âofâ16), etc.,
can be achieved by using other MC14555B or MC14556B devices.
Applications include code conversion, address decoding, memory
selection control, and demultiplexing (using the Enable input as a data
input) in digital data transmission systems.
⢠Diode Protection on All Inputs
⢠Active High or Active Low Outputs
⢠Expandable
⢠Supply Voltage Range = 3.0 Vdc to 18 Vdc
⢠All Outputs Buffered
⢠Capable of Driving Two LowâPower TTL Loads or One LowâPower
Schottky TTL Load Over the Rated Temperature Range
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
Symbol
Parameter
Value
Unit
VDD
DC Supply Voltage Range
â 0.5 to +18.0
V
Vin, Vout Input or Output Voltage Range â 0.5 to VDD + 0.5
V
(DC or Transient)
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
± 10
mA
PD
Power Dissipation,
per Package (Note 3.)
500
mW
TA
Ambient Temperature Range
Tstg
Storage Temperature Range
TL
Lead Temperature
(8âSecond Soldering)
â 55 to +125
°C
â 65 to +150
°C
260
°C
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic âP and D/DWâ Packages: â 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
v v highâimpedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
PDIPâ16
P SUFFIX
CASE 648
SOICâ16
D SUFFIX
CASE 751B
SOEIAJâ16
F SUFFIX
CASE 966
MARKING
DIAGRAMS
16
MC1455XBCP
AWLYYWW
1
16
1455XB
AWLYWW
1
16
MC1455XB
AWLYWW
1
X
= Specific Device Code
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC14555BCP
PDIPâ16
2000/Box
MC14555BD
SOICâ16
48/Rail
MC14555BDR2 SOICâ16 2500/Tape & Reel
MC14555BF
SOEIAJâ16 See Note 1.
MC14555BFEL SOEIAJâ16 See Note 1.
MC14556BCP
PDIPâ16
2000/Box
MC14556BD
SOICâ16
48/Rail
MC14556BDR2 SOICâ16 2500/Tape & Reel
MC14556BF
SOEIAJâ16 See Note 1.
MC14556BFEL SOEIAJâ16 See Note 1.
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
© Semiconductor Components Industries, LLC, 2000
1
March, 2000 â Rev. 3
Publication Order Number:
MC14555B/D
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