MC14553B_06 Datasheet, PDF (1/8 Pages) ON Semiconductor – 3−Digit BCD Counter

MC14553B
3−Digit BCD Counter
The MC14553B 3−digit BCD counter consists of 3 negative edge
triggered BCD counters that are cascaded synchronously. A quad latch
at the output of each counter permits storage of any given count. The
information is then time division multiplexed, providing one BCD
number or digit at a time. Digit select outputs provide display control.
All outputs are TTL compatible.
An on−chip oscillator provides the low−frequency scanning clock
which drives the multiplexer output selector.
This device is used in instrumentation counters, clock displays,
digital panel meters, and as a building block for general logic
applications.
Features
• TTL Compatible Outputs
• On−Chip Oscillator
• Cascadable
• Clock Disable Input
• Pulse Shaping Permits Very Slow Rise Times on Input Clock
• Output Latches
• Master Reset
• Pb−Free Packages are Available*
MAXIMUM RATINGS (Voltages Referenced to V_SS)
Parameter
Symbol
Value
Unit
DC Supply Voltage Range
V_DD −0.5 to +18.0 V
Input or Output Voltage Range
(DC or Transient)
V_in,
−0.5 to V_DD V
V_out
+ 0.5
Input Current (DC or Transient) per Pin
I_in
±10
mA
Output Current (DC or Transient) per Pin
I_out
+20
mA
Power Dissipation, per Package (Note 1)
P_D
500
mW
Ambient Temperature Range
T_A
−55 to +125 °C
Storage Temperature Range
T_stg −65 to +150 °C
Lead Temperature (8−Second Soldering)
T_L
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating: Plastic “P and D/DW”
Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V_in and V_out should be constrained to
the range V_SS v (V_in or V_out) v V_DD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V_SS or V_DD). Unused outputs must be left open.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
1
June, 2006 − Rev. 7
http://onsemi.com
MARKING
DIAGRAMS
PDIP−16 ¹⁶
P SUFFIX
CASE 648
1
MC14553BCP
AWLYYWWG
1
16
SO−16W
DW SUFFIX
1
CASE 751G
MC14553B
AWLYYWW
1
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
4
3
CIA CIB Q0
9
12
CLOCK
Q1
7
10
LE
11
DIS
13
MR
Q2
6
Q3
5
O.F.
14
DS1
2
DS2
1
DS3
15
V_DD = PIN 16
V_SS = PIN 8
Figure 1. Block Diagram
ORDERING INFORMATION
Device
MC14553BCP
MC14553BCPG
MC14553BDW
Package
PDIP−16
PDIP−16
(Pb−Free)
SOIC−16
Shipping
25 Units / Rail
25 Units / Rail
47 Units / Rail
Publication Order Number:
MC14553B/D