MC1455 Datasheet, PDF (1/10 Pages) ON Semiconductor – Timers

MC1455, MC1455B,
NCV1455B
Timers
The MC1455 monolithic timing circuit is a highly stable controller
capable of producing accurate time delays or oscillation. Additional
terminals are provided for triggering or resetting if desired. In the time
delay mode, time is precisely controlled by one external resistor and
capacitor. For astable operation as an oscillator, the free−running
frequency and the duty cycle are both accurately controlled with two
external resistors and one capacitor. The circuit may be triggered and
reset on falling waveforms, and the output structure can source or sink
up to 200 mA or drive MTTL circuits.
• Direct Replacement for NE555 Timers
• Timing from Microseconds through Hours
• Operates in Both Astable and Monostable Modes
• Adjustable Duty Cycle
• High Current Output Can Source or Sink 200 mA
• Output Can Drive MTTL
• Temperature Stability of 0.005% per °C
• Normally ON or Normally OFF Output
10 k
0.1 mF
5
0.01 mF
1.0 k
38
4
6R
2 _{MC1455 7}
1 ^{1.0 mF}
MT2
20 M ^G
C
−10 V
Load
MT1
1N4003
t = 1.1; R and C = 22 sec
Time delay (t) is variable by
changing R and C (see Figure 16).
1N4740
3.5 k
−
10
mF
250 V +
http://onsemi.com
MARKING
DIAGRAMS
8
1
P1 SUFFIX
PLASTIC PACKAGE
CASE 626
XXXXXXXXX
AWL
YYWW
8
1
D SUFFIX
PLASTIC PACKAGE
CASE 751
8
XXXXXX
ALYW
1
xx
= Specific Device Code
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page ___ of this data sheet.
(Create − Named − OrderingInfoText.)
Figure 1. 22 Second Solid State Time Delay Relay Circuit
V_R
I_CC
V_CC
V_CC
8
5k
6
Threshold
5
Control Voltage
5k
Trigger
2
5k
+
Comp
−A
+
Comp
−B
1
Gnd
Flip
R _Flop
Q
S ^Inhibit/
Reset
4
Reset
7
Discharge
3
Output
+
0.01 mF
V_O
Reset 4 8
700
5
V_CC ⁷
Control
Voltage
Discharge
MC1455
3
Threshold
Output
I_Sink
I_Source
6
I_th
Gnd Trigger
12
2.0 k ^VS
Test circuit for measuring DC parameters (to set output and
measure parameters):
a) When V_S w 2/3 V_CC, V_O is low.
b) When V_S v 1/3 V_CC, V_O is high.
c) When V_O is low, Pin 7 sinks current. To test for Reset, set V_O
c) high, apply Reset voltage, and test for current flowing into Pin 7.
c) When Reset is not in use, it should be tied to V_CC.
Figure 2. Representative Block Diagram
Figure 3. General Test Circuit
© Semiconductor Components Industries, LLC, 2004
1
March, 2004 − Rev. 8
Publication Order Number:
MC1455/D