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MC14517B_14 Datasheet, PDF (1/5 Pages) ON Semiconductor – Dual 64-Bit Static Shift Register | |||
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MC14517B
Dual 64-Bit Static Shift
Register
The MC14517B dual 64âbit static shift register consists of two
identical, independent, 64âbit registers. Each register has separate clock
and write enable inputs, as well as outputs at bits 16, 32, 48, and 64. Data
at the data input is entered by clocking, regardless of the state of the write
enable input. An output is disabled (open circuited) when the write enable
input is high. During this time, data appearing at the data input as well as
the 16âbit, 32âbit, and 48âbit taps may be entered into the device by
application of a clock pulse. This feature permits the register to be loaded
with 64 bits in 16 clock periods, and also permits bus logic to be used.
This device is useful in time delay circuits, temporary memory storage
circuits, and other serial shift register applications.
Features
⢠Diode Protection on All Inputs
⢠Fully Static Operation
⢠Output Transitions Occur on the Rising Edge of the Clock Pulse
⢠Exceedingly Slow Input Transition Rates May Be Applied to the
Clock Input
⢠3âState Output at 64thâBit Allows Use in Bus Logic Applications
⢠Shift Registers of any Length may be Fully Loaded with 16 Clock
Pulses
⢠Supply Voltage Range = 3.0 Vdc to 18 Vdc
⢠Capable of Driving Two LowâPower TTL Loads or One LowâPower
Schottky TTL Load Over the Rated Temperature Range
⢠NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AECâQ100
Qualified and PPAP Capable
⢠This Device is PbâFree and is RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to VSS)
Parameter
Symbol
Value
Unit
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
VDD â0.5 to +18.0 V
Vin, Vout â0.5 to VDD V
+ 0.5
Input or Output Current (DC or Transient) Iin, Iout
±10
mA
per Pin
Power Dissipation per Package (Note 1)
PD
500
mW
Operating Temperature Range
TA
â55 to +125 °C
Storage Temperature Range
Tstg â 65 to +150 °C
Lead Temperature (8âSecond Soldering)
TL
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: Plastic âD/DWâ Package: â7.0 mW/_C From 65_C to
125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
highâimpedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS ⤠(Vin or Vout) ⤠VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
1
SOICâ16 WB
DW SUFFIX
CASE 751G
MARKING DIAGRAM
16
14517B
AWLYYWWG
1
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G
= PbâFree Package
PIN ASSIGNMENT
Q16A 1
Q48A 2
WEA 3
CA 4
Q64A 5
Q32A 6
DA 7
VSS 8
16 VDD
15 Q16B
14 Q48B
13 WEB
12 CB
11 Q64B
10 Q32B
9 DB
ORDERING INFORMATION
Device
Package
Shippingâ
MC14517BDWG
MC14517BDWR2G
SOICâ16 WB
(PbâFree)
SOICâ16 WB
(PbâFree)
47 Units/Rail
1000 /
Tape & Reel
NLV14517BDWR2G SOICâ16 WB 1000 /
(PbâFree) Tape & Reel
â For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2014
1
July, 2014 â Rev. 9
Publication Order Number:
MC14517B/D
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