MC14517B_06 Datasheet, PDF (1/6 Pages) ON Semiconductor – Dual 64−Bit Static Shift Register

MC14517B
Dual 64−Bit Static Shift
Register
The MC14517B dual 64−bit static shift register consists of two
identical, independent, 64−bit registers. Each register has separate clock
and write enable inputs, as well as outputs at bits 16, 32, 48, and 64. Data
at the data input is entered by clocking, regardless of the state of the write
enable input. An output is disabled (open circuited) when the write enable
input is high. During this time, data appearing at the data input as well as
the 16−bit, 32−bit, and 48−bit taps may be entered into the device by
application of a clock pulse. This feature permits the register to be loaded
with 64 bits in 16 clock periods, and also permits bus logic to be used.
This device is useful in time delay circuits, temporary memory storage
circuits, and other serial shift register applications.
Features
• Diode Protection on All Inputs
• Fully Static Operation
• Output Transitions Occur on the Rising Edge of the Clock Pulse
• Exceedingly Slow Input Transition Rates May Be Applied to the
Clock Input
• 3−State Output at 64th−Bit Allows Use in Bus Logic Applications
• Shift Registers of any Length may be Fully Loaded with 16 Clock
Pulses
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load Over the Rated Temperature Range
• Pb−Free Packages are Available*
MAXIMUM RATINGS (Voltages Referenced to V_SS)
Parameter
Symbol
Value
Unit
DC Supply Voltage Range
V_DD −0.5 to +18.0 V
Input or Output Voltage Range
(DC or Transient)
V_in, V_out −0.5 to V_DD V
+ 0.5
http://onsemi.com
MARKING
DIAGRAMS
16
PDIP−16
MC14516BCP
1
P SUFFIX
AWLYYWWG
CASE 648 ₁
16
SOIC−16
1
DW SUFFIX
CASE 751G
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G
= Pb−Free Package
14517B
AWLYYWWG
1
PIN ASSIGNMENT
Q16_A 1
Q48_A 2
WE_A 3
C_A 4
Q64_A 5
Q32_A 6
D_A 7
V_SS 8
16 V_DD
15 Q16_B
14 Q48_B
13 WE_B
12 C_B
11 Q64_B
10 Q32_B
9 D_B
Input or Output Current (DC or Transient) I_in, I_out
± 10
mA
per Pin
Power Dissipation per Package (Note 1)
P_D
500
mW
Operating Temperature Range
T_A
−55 to +125 °C
Storage Temperature Range
T_stg −65 to +150 °C
Lead Temperature (8−Second Soldering)
T_L
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating: Plastic “P and D/DW”
Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V_in and V_out should be constrained
to the range V_SS v (V_in or V_out) v V_DD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V_SS or V_DD). Unused outputs must be left open.
ORDERING INFORMATION
Device
Package
Shipping^†
MC14517BCP
MC14517BCPG
PDIP−16
PDIP−16
(Pb−Free)
25 Units/Rail
25 Units/Rail
MC14517BDW
SOIC−16
47/Rail
MC14517BDWG
SOIC−16
(Pb−Free)
47/Rail
MC14517BDWR2 SOIC−16 1000/Tape & Reel
MC14517BDWR2G SOIC−16 1000/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
1
June, 2006 − Rev. 6
Publication Order Number:
MC14517B/D