MC14516B_06 Datasheet, PDF (1/11 Pages) ON Semiconductor – Binary Up/Down Counter

MC14516B
Binary Up/Down Counter
The MC14516B synchronous up/down binary counter is
constructed with MOS P−channel and N−channel enhancement mode
devices in a monolithic structure.
This counter can be preset by applying the desired value, in binary,
to the Preset inputs (P0, P1, P2, P3) and then bringing the Preset
Enable (PE) high. The direction of counting is controlled by applying
a high (for up counting) or a low (for down counting) to the
UP/DOWN input. The state of the counter changes on the positive
transition of the clock input.
Cascading can be accomplished by connecting the Carry Out to the
Carry In of the next stage while clocking each counter in parallel. The
outputs (Q0, Q1, Q2, Q3) can be reset to a low state by applying a high
to the reset (R) pin.
This CMOS counter finds primary use in up/down and difference
counting. Other applications include: (1) Frequency synthesizer
applications where low power dissipation and/or high noise immunity
is desired, (2) Analog−to−Digital and Digital−to−Analog conversions,
and (3) Magnitude and sign generation.
Features
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Internally Synchronous for High Speed
• Logic Edge−Clocked Design — Count Occurs on Positive Going
Edge of Clock
• Single Pin Reset
• Asynchronous Preset Enable Operation
• Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky Load Over the Rated Temperature Range
• Pb−Free Packages are Available*
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1
http://onsemi.com
MARKING
DIAGRAMS
PDIP−16 ¹⁶
P SUFFIX
CASE 648
1
MC14516BCP
AWLYYWWG
16
SOIC−16
D SUFFIX
CASE 751B
1
14516BG
AWLYWW
16
SOEIAJ−16
F SUFFIX
CASE 966
MC14516B
ALYWG
1
1
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G
= Pb−Free Package
MAXIMUM RATINGS (Voltages Referenced to V_SS)
Parameter
Symbol
Value
Unit
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
V_DD −0.5 to +18.0 V
V_in, V_out −0.5 to V_DD V
+ 0.5
Input or Output Current (DC or Transient) I_in, I_out
± 10
mA
per Pin
Power Dissipation, per Package (Note 1) P_D
500
mW
Ambient Temperature Range
T_A
−55 to +125 °C
Storage Temperature Range
T_stg
−65 to +150 °C
Lead Temperature (8−Second Soldering)
T_L
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating: Plastic “P and D/DW”
Packages: – 7.0 mW/_C From 65_C To 125_C
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
This device contains protection circuitry to guard
against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated
voltages to this high−impedance circuit. For proper
operation, V_in and V_out should be constrained to the
range V_SS v (V_in or V_out) v V_DD.
Unused inputs must always be tied to an appropriate
logic voltage level (e.g., either V_SS or V_DD). Unused
outputs must be left open.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
1
June, 2006 − Rev. 7
Publication Order Number:
MC14516B/D