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MC14514B_06 Datasheet, PDF (1/8 Pages) ON Semiconductor – 4−Bit Transparent Latch / 4−to−16 Line Decoder | |||
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MC14514B, MC14515B
4âBit Transparent Latch /
4âtoâ16 Line Decoder
The MC14514B and MC14515B are two output options of a 4 to 16
line decoder with latched inputs. The MC14514B (output active high
option) presents a logical â1â at the selected output, whereas the
MC14515B (output active low option) presents a logical â0â at the
selected output. The latches are RâS type flipâflops which hold the
last input data presented prior to the strobe transition from â1â to â0â.
These high and low options of a 4âbit latch / 4 to 16 line decoder are
constructed with Nâchannel and Pâchannel enhancement mode
devices in a single monolithic structure. The latches are RâS type
flipâflops and data is admitted upon a signal incident at the strobe
input, decoded, and presented at the output.
These complementary circuits find primary use in decoding
applications where low power dissipation and/or high noise immunity
is desired.
Features
⢠Supply Voltage Range = 3.0 Vdc to 18 Vdc
⢠Capable of Driving Two Lowâpower TTL Loads or One Lowâpower
Schottky TTL Load the Rated Temperature Range
⢠PbâFree Packages are Available*
MAXIMUM RATINGS (Voltages Referenced to VSS)
Parameter
Symbol
Value
Unit
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
VDD â0.5 to +18.0 V
Vin, Vout â 0.5 to VDD V
+0.5
Input or Output Current (DC or Transient) Iin, Iout
per Pin
± 10
mA
Power Dissipation per Package (Note 1)
PD
500
mW
Ambient Temperature Range
TA
â55 to +125 °C
Storage Temperature Range
Tstg
â65 to +150 °C
Lead Temperature (8âSecond Soldering)
TL
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating: Plastic âP and D/DWâ
Packages: â 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
highâimpedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
MARKING
DIAGRAMS
24
1
PDIPâ24
P SUFFIX
CASE 709
MC145xxBCP
AWLYYWWG
1
24
SOICâ24
1
DW SUFFIX
MC145xxB
AWLYYWWG
CASE 751E
1
xx = 14 or 15
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = PbâFree Package
PIN ASSIGNMENT
ST 1
D1 2
D2 3
S7 4
S6 5
S5 6
S4 7
S3 8
S1 9
S2 10
S0 11
VSS 12
24 VDD
23 INH
22 D4
21 D3
20 S10
19 S11
18 S8
17 S9
16 S14
15 S15
14 S12
13 S13
*For additional information on our PbâFree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
1
June, 2006 â Rev. 6
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
Publication Order Number:
MC14514B/D
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