MC14504B Datasheet, PDF (1/8 Pages) ON Semiconductor – Hex Level Shifter for TTL to CMOS or COMS to CMOS

MC14504B
Hex Level Shifter for TTL to
CMOS or CMOS to CMOS
The MC14504B is a hex non–inverting level shifter using CMOS
technology. The level shifter will shift a TTL signal to CMOS logic
levels for any CMOS supply voltage between 5 and 15 volts. A control
input also allows interface from CMOS to CMOS at one logic level to
another logic level: Either up or down level translating is
accomplished by selection of power supply levels V_DD and V_CC. The
V_CC level sets the input signal levels while V_DD selects the output
voltage levels.
• UP Translates from a Low to a High Voltage or DOWN Translates
from a High to a Low Voltage
• Input Threshold Can Be Shifted for TTL Compatibility
• No Sequencing Required on Power Supplies or Inputs for Power Up
or Power Down
• 3 to 18 Vdc Operation for V_DD and V_CC
• Diode Protected Inputs to V_SS
• Capable of Driving Two Low–Power TTL Loads or One Low–Power
Schottky TTL Load Over the Rated Temperature Range
MAXIMUM RATINGS (Voltages Referenced to V_SS) (Note 2.)
Symbol
Parameter
Value
Unit
V_CC
DC Supply Voltage Range
V_DD
DC Supply Voltage Range
V_in
Input Voltage Range
(DC or Transient)
– 0.5 to +18.0
V
– 0.5 to +18.0
V
– 0.5 to +18.0
V
V_out
Output Voltage Range
(DC or Transient)
– 0.5 to V_DD + 0.5
V
I_in, I_out
Input or Output Current
(DC or Transient) per Pin
± 10
mA
P_D
Power Dissipation,
per Package (Note 3.)
500
mW
T_A
Ambient Temperature Range
T_stg
Storage Temperature Range
T_L
Lead Temperature
(8–Second Soldering)
– 55 to +125
°C
– 65 to +150
°C
260
°C
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
v v ^{high–impedance circuit. For proper operation, Vin and Vout should be constrained}
to the range V_SS (V_in or V_out) V_DD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V_SS or V_DD). Unused outputs must be left open.
http://onsemi.com
PDIP–16
P SUFFIX
CASE 648
MARKING
DIAGRAMS
16
MC14504BCP
AWLYYWW
1
SOIC–16
D SUFFIX
CASE 751B
16
14504B
AWLYWW
1
TSSOP–16
DT SUFFIX
CASE 948F
16
14
504B
ALYW
1
SOEIAJ–16
F SUFFIX
CASE 966
16
MC14504B
AWLYWW
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC14504BCP
PDIP–16
2000/Box
MC14504BD
SOIC–16
48/Rail
MC14504BDR2 SOIC–16 2500/Tape & Reel
MC14504BDT
TSSOP–16
96/Rail
MC14504BF
SOEIAJ–16 See Note 1.
MC14504BFEL SOEIAJ–16 See Note 1.
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
© Semiconductor Components Industries, LLC, 2000
1
March, 2000 – Rev. 3
Publication Order Number:
MC14504B/D