MC14503B_14 Datasheet, PDF (1/5 Pages) ON Semiconductor – Hex Non-Inverting 3-State Buffer

MC14503B
Hex Non-Inverting 3-State
Buffer
The MC14503B is a hex non−inverting buffer with 3−state outputs,
and a high current source and sink capability. The 3−state outputs
make it useful in common bussing applications. Two disable controls
are provided. A high level on the Disable A input causes the outputs of
buffers 1 through 4 to go into a high impedance state and a high level
on the Disable B input causes the outputs of buffers 5 and 6 to go into
a high impedance state.
Features
• 3−State Outputs
• TTL Compatible − Will Drive One TTL Load Over Full Temperature
Range
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Two Disable Controls for Added Versatility
• Pin for Pin Replacement for MM80C97 and 340097
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• This Device is Pb−Free and is RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to V_SS) (Note 1)
Parameter
Symbol
Value
Unit
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
V_DD −0.5 to +18.0 V
V_in, V_out − 0.5 to V_DD
V
+ 0.5
Input Current (DC or Transient) per Pin
I_in
±10
mA
Output Current (DC or Transient) per Pin
I_out
±25
mA
Power Dissipation, per Package (Note 2)
P_D
500
mW
Ambient Temperature Range
T_A
−55 to +125 °C
Storage Temperature Range
−65 to +150 °C
Lead Temperature (8−Second Soldering)
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Maximum Ratings are those values beyond which damage to the device may
occur.
2. Temperature Derating:
“D/DW” Package: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V_in and V_out should be constrained
to the range V_SS ≤ (V_in or V_out) ≤ V_DD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V_SS or V_DD). Unused outputs must be left open.
http://onsemi.com
1
SOIC−16
D SUFFIX
CASE 751B
PIN ASSIGNMENT
DIS A 1
IN 1 2
OUT 1 3
IN 2 4
OUT 2 5
IN 3 6
OUT 3 7
V_SS 8
16 V_DD
15 DIS B
14 IN 6
13 OUT 6
12 IN 5
11 OUT 5
10 IN 4
9 OUT 4
MARKING DIAGRAM
16
14503BG
AWLYWW
1
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G
= Pb−Free Package
TRUTH TABLE
Appropriate
Disable
In_n
Input
0
0
1
0
X
1
X = Don’t Care
Out_n
0
1
High
Impedance
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
1
July, 2014 − Rev. 10
Publication Order Number:
MC14503B/D