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MC14503B_06 Datasheet, PDF (1/7 Pages) ON Semiconductor – Hex Non−Inverting 3−State Buffer | |||
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MC14503B
Hex NonâInverting 3âState
Buffer
The MC14503B is a hex nonâinverting buffer with 3âstate outputs,
and a high current source and sink capability. The 3âstate outputs
make it useful in common bussing applications. Two disable controls
are provided. A high level on the Disable A input causes the outputs of
buffers 1 through 4 to go into a high impedance state and a high level
on the Disable B input causes the outputs of buffers 5 and 6 to go into a
high impedance state.
Features
⢠3âState Outputs
⢠TTL Compatible â Will Drive One TTL Load Over Full
Temperature Range
⢠Supply Voltage Range = 3.0 Vdc to 18 Vdc
⢠Two Disable Controls for Added Versatility
⢠Pin for Pin Replacement for MM80C97 and 340097
⢠PbâFree Packages are Available*
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1)
Parameter
Symbol
Value
Unit
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
VDD â0.5 to +18.0 V
Vin, Vout â 0.5 to VDD V
+ 0.5
Input Current (DC or Transient) per Pin
Iin
± 10
mA
Output Current (DC or Transient) per Pin
Iout
± 25
mA
Power Dissipation, per Package (Note 2)
PD
500
mW
Ambient Temperature Range
TA
â55 to +125 °C
Storage Temperature Range
â65 to +150 °C
Lead Temperature (8âSecond Soldering)
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Maximum Ratings are those values beyond which damage to the device may
occur.
2. Temperature Derating:
Plastic âP and D/DWâ Packages: â 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
highâimpedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
1
1
http://onsemi.com
MARKING
DIAGRAMS
PDIPâ16
P SUFFIX
16
MC14503BCP
AWLYYWWG
CASE 648
1
SOICâ16 16
D SUFFIX
CASE 751B
1
14503BG
AWLYWW
16
SOEIAJâ16
F SUFFIX
CASE 966
MC14503B
ALYWG
1
1
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G
= PbâFree Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
*For additional information on our PbâFree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
1
June, 2006 â Rev. 7
Publication Order Number:
MC14503B/D
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