MC14490_06 Datasheet, PDF (1/11 Pages) ON Semiconductor – Hex Contact Bounce Eliminator

MC14490
Hex Contact Bounce
Eliminator
The MC14490 is constructed with complementary MOS enhancement
mode devices, and is used for the elimination of extraneous level changes
that result when interfacing with mechanical contacts. The digital contact
bounce eliminator circuit takes an input signal from a bouncing contact
and generates a clean digital signal four clock periods after the input has
stabilized. The bounce eliminator circuit will remove bounce on both the
“make” and the “break” of a contact closure. The clock for operation of
the MC14490 is derived from an internal R−C oscillator which requires
only an external capacitor to adjust for the desired operating frequency
(bounce delay). The clock may also be driven from an external clock
source or the oscillator of another MC14490 (see Figure 5).
NOTE: Immediately after powerup, the outputs of the MC14490 are in
indeterminate states.
Features
• Diode Protection on All Inputs
• Six Debouncers Per Package
• Internal Pullups on All Data Inputs
• Can Be Used as a Digital Integrator, System Synchronizer, or Delay Line
• Internal Oscillator (R−C), or External Clock Source
• TTL Compatible Data Inputs/Outputs
• Single Line Input, Debounces Both “Make” and “Break” Contacts
• Does Not Require “Form C” (Single Pole Double Throw) Input Signal
• Cascadable for Longer Time Delays
• Schmitt Trigger on Clock Input (Pin 7)
• Supply Voltage Range = 3.0 V to 18 V
• Chip Complexity: 546 FETs or 136.5 Equivalent Gates
• Pb−Free Packages are Available*
MAXIMUM RATINGS (Voltages Referenced to V_SS)
Parameter
Symbol
Value
Unit
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
V_DD −0.5 to +18.0 V
V_in, V_out −0.5 to V_DD V
+ 0.5
Input Current (DC or Transient) per Pin
I_in
± 10
mA
Power Dissipation, per Package (Note 1) P_D
500
mW
Ambient Temperature Range
T_A
−55 to +125 °C
Storage Temperature Range
T_stg
−65 to +150 °C
Lead Temperature (8−Second Soldering)
T_L
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating: Plastic “P and D/DW”
Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V_in and V_out should be constrained
to the range V_SS v (V_in or V_out) v V_DD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V_SS or V_DD). Unused outputs must be left open.
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MARKING
DIAGRAMS
PDIP−16 ¹⁶
P SUFFIX
CASE 648
1
MC14490P
AWLYYWWG
16
SOIC−16
DW SUFFIX
CASE 751G
14490
AWLYYWWG
1
16
SOEIAJ−16
F SUFFIX
CASE 966
MC14490
ALYWG
1
1
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
*For additional information on our Pb−Free strategy
and soldering details, please download the
ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
1
June, 2006 − Rev. 7
Publication Order Number:
MC14490/D