MC14175B_14 Datasheet, PDF (1/6 Pages) ON Semiconductor – Quad Type D Flip-Flop

MC14175B
Quad Type D Flip-Flop
The MC14175B quad type D flip−flop is constructed with MOS
P−channel and N−channel enhancement mode devices in a single
monolithic structure. Each of the four flip−flops is positive−edge
triggered by a common clock input (C). An active−low reset input (R)
asynchronously resets all flip−flops. Each flip−flop has independent
Data (D) inputs and complementary outputs (Q and Q). These devices
may be used as shift register elements or as type T flip−flops for
counter and toggle applications.
Features
• Complementary Outputs
• Static Operation
• All Inputs and Outputs Buffered
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Output Compatible with Two Low−Power TTL Loads or One
Low−Power Schottky TTL Load
• Functional Equivalent to TTL 74175
• These Devices are Pb−Free and are RoHS Compliant
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable*
MAXIMUM RATINGS (Voltages Referenced to V_SS)
Parameter
Symbol
Value
Unit
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
V_DD −0.5 to +18.0 V
V_in, V_out − 0.5 to V_DD
V
+ 0.5
Input or Output Current (DC or Transient) I_in, I_out
±10
mA
per Pin
Power Dissipation per Package (Note 1)
Ambient Temperature Range
Storage Temperature Range
P_D
500
mW
T_A
−55 to +125 °C
−65 to +150 °C
Lead Temperature (8−Second Soldering)
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V_in and V_out should be constrained
to the range V_SS ≤ (V_in or V_out) ≤ V_DD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V_SS or V_DD). Unused outputs must be left open.
© Semiconductor Components Industries, LLC, 2014
1
August, 2014 − Rev. 9
http://onsemi.com
SOIC−16
D SUFFIX
CASE 751B
SOEIAJ−16
F SUFFIX
CASE 966
PIN ASSIGNMENT
R1
Q0 2
Q0 3
D0 4
D1 5
Q1 6
Q1 7
V_SS 8
16 V_DD
15 Q3
14 Q3
13 D3
12 D2
11 Q2
10 Q2
9C
MARKING DIAGRAMS
16
14175BG
AWLYWW
1
SOIC−16
16
MC14175B
ALYWG
1
SOEIAJ−16
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G
= Pb−Free Package
ORDERING INFORMATION
Device
Package
Shipping^†
MC14175BDG
SOIC−16
(Pb−Free)
48 Units/Rail
MC14175BDR2G SOIC−16
(Pb−Free)
NLV14175BDR2G* SOIC−16
(Pb−Free)
2500/Tape & Reel
2500/Tape & Reel
MC14175BFELG SOEIAJ−16 2000/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Publication Order Number:
MC14175B/D