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MC14174B_13 Datasheet, PDF (1/6 Pages) ON Semiconductor – Hex Type D Flip-Flop | |||
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MC14174B
Hex Type D Flip-Flop
The MC14174B hex type D flipâflop is constructed with MOS
Pâchannel and Nâchannel enhancement mode devices in a single
monolithic structure. Data on the D inputs which meets the setup time
requirements is transferred to the Q outputs on the positive edge of the
clock pulse. All six flipâflops share common clock and reset inputs.
The reset is active low, and independent of the clock.
Features
⢠Static Operation
⢠All Inputs and Outputs Buffered
⢠Diode Protection on All Inputs
⢠Supply Voltage Range = 3.0 Vdc to 18 Vdc
⢠Capable of Driving Two LowâPower TTL Loads or One LowâPower
Schottky TTL Load Over the Rated Temperature Range
1
⢠Functional Equivalent to TTL 74174
⢠These Devices are PbâFree and are RoHS Compliant
⢠NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AECâQ100
Qualified and PPAP Capable
1
http://onsemi.com
MARKING
DIAGRAMS
PDIPâ16
P SUFFIX
16
MC14174BCP
AWLYYWWG
CASE 648
1
SOICâ16 16
D SUFFIX
CASE 751B
1
14174BG
AWLYWW
MAXIMUM RATINGS (Voltages Referenced to VSS)
Parameter
Symbol
Value
Unit
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
VDD â0.5 to +18.0 V
Vin, Vout â 0.5 to VDD
V
+ 0.5
Input or Output Current (DC or Transient) Iin, Iout
± 10
mA
per Pin
Power Dissipation, per Package (Note 1)
PD
500
mW
Ambient Temperature Range
TA
â55 to +125 °C
Storage Temperature Range
â65 to +150 °C
Lead Temperature (8âSecond Soldering)
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating: Plastic âP and D/DWâ
Packages: â 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
highâimpedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
A = Assembly Location
WL = Wafer Lot
YY, Y = Year
WW = Work Week
G = PbâFree Package
ORDERING INFORMATION
Device
Package
Shippingâ
MC14174BCPG
MC14174BDR2G
PDIPâ16
(PbâFree)
SOICâ16
(PbâFree)
500 Units/Rail
2500/Tape & Reel
NLV14174BDR2G SOICâ16 2500/Tape & Reel
(PbâFree)
â For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2013
1
May, 2013 â Rev. 8
Publication Order Number:
MC14174B/D
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