MC14174B_11 Datasheet, PDF (1/6 Pages) ON Semiconductor – Hex Type D Flip-Flop

MC14174B
Hex Type D Flip-Flop
The MC14174B hex type D flip−flop is constructed with MOS
P−channel and N−channel enhancement mode devices in a single
monolithic structure. Data on the D inputs which meets the setup time
requirements is transferred to the Q outputs on the positive edge of the
clock pulse. All six flip−flops share common clock and reset inputs.
The reset is active low, and independent of the clock.
Features
• Static Operation
• All Inputs and Outputs Buffered
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load Over the Rated Temperature Range
• Functional Equivalent to TTL 74174
• These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to V_SS)
Parameter
Symbol
Value
Unit
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
V_DD −0.5 to +18.0 V
V_in, V_out − 0.5 to V_DD
V
+ 0.5
Input or Output Current (DC or Transient) I_in, I_out
± 10
mA
per Pin
Power Dissipation, per Package (Note 1)
P_D
500
mW
Ambient Temperature Range
T_A
−55 to +125 °C
Storage Temperature Range
−65 to +150 °C
Lead Temperature (8−Second Soldering)
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating: Plastic “P and D/DW”
Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V_in and V_out should be constrained
to the range V_SS v (V_in or V_out) v V_DD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V_SS or V_DD). Unused outputs must be left open.
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MARKING
DIAGRAMS
PDIP−16
P SUFFIX
16
MC14174BCP
AWLYYWWG
CASE 648
1
SOIC−16 ¹⁶
D SUFFIX
CASE 751B
1
14174BG
AWLYWW
A = Assembly Location
WL = Wafer Lot
YY, Y = Year
WW = Work Week
G = Pb−Free Package
ORDERING INFORMATION
Device
Package
MC14174BCPG
MC14174BDG
PDIP−16
(Pb−Free)
SOIC−16
(Pb−Free)
MC14174BDR2G SOIC−16
(Pb−Free)
Shipping^†
500 Units/Rail
48 Units/Rail
2500/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2011
1
June, 2011 − Rev. 7
Publication Order Number:
MC14174B/D