MC14099B_14 Datasheet, PDF (1/7 Pages) ON Semiconductor – 8-Bit Addressable Latches

MC14099B
8-Bit Addressable Latches
The MC14099B is an 8−bit addressable latch. Data is entered in
serial form when the appropriate latch is addressed (via address pins
A0, A1, A2) and write disable is in the low state. For the MC14099B
the input is a unidirectional write only port.
The data is presented in parallel at the output of the eight latches
independently of the state of Write Disable, Write/Read or Chip
Enable.
A Master Reset capability is available on both parts.
Features
• Serial Data Input
• Parallel Output
• Master Reset
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low−power TTL Loads or One
Low−Power Schottky TTL Load over the Rated Temperature
Range
• MC14099B pin for pin compatible with CD4099B
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• This Device is Pb−Free and is RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to V_SS)
Symbol
Parameter
Value
Unit
V_DD
V_in, V_out
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
−0.5 to +18.0
V
−0.5 to V_DD + 0.5
V
I_in, I_out
Input or Output Current
(DC or Transient) per Pin
±10
mA
P_D
Power Dissipation, per Package
(Note 1)
500
mW
T_A
Ambient Temperature Range
−55 to +125
°C
T_stg
Storage Temperature Range
−65 to +150
°C
T_L
Lead Temperature
(8−Second Soldering)
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V_in and V_out should be constrained
to the range V_SS ≤ (V_in or V_out) ≤ V_DD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V_SS or V_DD). Unused outputs must be left open.
http://onsemi.com
SOIC−16 WD
DW SUFFIX
CASE 751G
PIN ASSIGNMENT
Q7 1
RESE 2
T
DATA 3
WRITE
DISABLE
4
A0 5
A1 6
A2 7
V_SS 8
16 V_DD
15 Q6
14 Q5
13 Q4
12 Q3
11 Q2
10 Q1
9 Q0
MARKING DIAGRAM
16
14099BG
AWLYYWW
1
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G
= Pb−Free Indicator
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
1
August, 2014 − Rev. 9
Publication Order Number:
MC14099B/D