MC14094B_05 Datasheet, PDF (1/10 Pages) ON Semiconductor – 8−Stage Shift/Store Register with Three−State Outputs

MC14094B
8−Stage Shift/Store Register
with Three−State Outputs
The MC14094B combines an 8−stage shift register with a data latch
for each stage and a 3−state output from each latch.
Data is shifted on the positive clock transition and is shifted from the
seventh stage to two serial outputs. The Q_S output data is for use in
high−speed cascaded systems. The Q_S output data is shifted on the
following negative clock transition for use in low−speed cascaded
systems.
Data from each stage of the shift register is latched on the negative
transition of the strobe input. Data propagates through the latch while
strobe is high.
Outputs of the eight data latches are controlled by 3−state buffers
which are placed in the high−impedance state by a logic Low on
Output Enable.
Features
• 3−State Outputs
• Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load Over the Rated Temperature Range
• Input Diode Protection
• Data Latch
• Dual Outputs for Data Out on Both Positive and
Negative Clock Transitions
• Useful for Serial−to−Parallel Data Conversion
• Pin−for−Pin Compatible with CD4094B
• Pb−Free Packages are Available*
MAXIMUM RATINGS (Voltages Referenced to V_SS)
Symbol
Parameter
Value
Unit
V_DD
V_in, V_out
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
−0.5 to +18.0
V
−0.5 to V_DD + 0.5
V
I_in, I_out
Input or Output Current
(DC or Transient) per Pin
± 10
mA
P_D
Power Dissipation, per Package
500
mW
(Note 1)
T_A
Ambient Temperature Range
T_stg
Storage Temperature Range
T_L
Lead Temperature
(8−Second Soldering)
−55 to +125
°C
−65 to +150
°C
260
°C
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V_in and V_out should be constrained
to the range V_SS v (V_in or V_out) v V_DD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V_SS or V_DD). Unused outputs must be left open.
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MARKING
DIAGRAMS
PDIP−16 ¹⁶
P SUFFIX
CASE 648
1
MC14094BCP
AWLYYWWG
SOIC−16
D SUFFIX
CASE 751B
16
14094BG
AWLYWW
1
TSSOP−16
DT SUFFIX
CASE 948F
16
14
094B
ALYW
1
SOEIAJ−16
F SUFFIX
CASE 966
16
MC14094B
ALYWG
1
A
WL, L
YY, Y
WW, W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Indicator
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
*For additional information on our Pb−Free strategy
and soldering details, please download the
ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2005
1
August, 2005 − Rev. 6
Publication Order Number:
MC14094B/D