MC14094B Datasheet, PDF (1/8 Pages) ON Semiconductor – 8-Stage Shift/Store Register with Three-State Outputs

MC14094B
8-Stage Shift/Store Register
with Three-State Outputs
The MC14094B combines an 8–stage shift register with a data latch
for each stage and a three–state output from each latch.
Data is shifted on the positive clock transition and is shifted from the
seventh stage to two serial outputs. The Q_S output data is for use in
high–speed cascaded systems. The Q′_S output data is shifted on the
following negative clock transition for use in low–speed cascaded
systems.
Data from each stage of the shift register is latched on the negative
transition of the strobe input. Data propagates through the latch while
strobe is high.
Outputs of the eight data latches are controlled by three–state
buffers which are placed in the high–impedance state by a logic Low
on Output Enable.
• Three–State Outputs
• Capable of Driving Two Low–Power TTL Loads or One Low–Power
Schottky TTL Load Over the Rated Temperature Range
• Input Diode Protection
• Data Latch
• Dual Outputs for Data Out on Both Positive and
Negative Clock Transitions
• Useful for Serial–to–Parallel Data Conversion
• Pin–for–Pin Compatible with CD4094B
MAXIMUM RATINGS (Voltages Referenced to V_SS) (Note 2.)
Symbol
Parameter
Value
Unit
V_DD
DC Supply Voltage Range
– 0.5 to +18.0
V
V_in, V_out Input or Output Voltage Range – 0.5 to V_DD + 0.5
V
(DC or Transient)
I_in, I_out
Input or Output Current
(DC or Transient) per Pin
± 10
mA
P_D
Power Dissipation,
per Package (Note 3.)
500
mW
T_A
Ambient Temperature Range
– 55 to +125
°C
T_stg
Storage Temperature Range
– 65 to +150
°C
T_L
Lead Temperature
(8–Second Soldering)
260
°C
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
v v ^{high–impedance circuit. For proper operation, Vin and Vout should be constrained}
to the range V_SS (V_in or V_out) V_DD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V_SS or V_DD). Unused outputs must be left open.
http://onsemi.com
PDIP–16
P SUFFIX
CASE 648
MARKING
DIAGRAMS
16
MC14094BCP
AWLYYWW
1
SOIC–16
D SUFFIX
CASE 751B
TSSOP–16
DT SUFFIX
CASE 948F
16
14094B
AWLYWW
1
16
14
094B
ALYW
SOEIAJ–16
F SUFFIX
CASE 966
1
16
MC14094B
AWLYWW
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC14094BCP
PDIP–16
2000/Box
MC14094BD
SOIC–16
48/Rail
MC14094BDR2 SOIC–16 2500/Tape & Reel
MC14094BDT TSSOP–16
96/Rail
MC14094BDTR2 TSSOP–16 2500/Tape & Reel
MC14094BF
SOEIAJ–16 See Note 1.
1. For ordering information on the EIAJ version of the
SOIC packages, please contact your local ON
Semiconductor representative.
© Semiconductor Components Industries, LLC, 2000
1
March, 2000 – Rev. 3
Publication Order Number:
MC14094B/D