MC14093B_14 Datasheet, PDF (1/8 Pages) ON Semiconductor – Quad 2-Input "NAND"

MC14093B
Quad 2-Input “NAND"
Schmitt Trigger
The MC14093B Schmitt trigger is constructed with MOS
P−channel and N−channel enhancement mode devices in a single
monolithic structure. These devices find primary use where low power
dissipation and/or high noise immunity is desired. The MC14093B
may be used in place of the MC14011B quad 2−input NAND gate for
enhanced noise immunity or to “square up” slowly changing
waveforms.
Features
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low−Power TTL Loads or One
Low−Power Schottky TTL Load Over the Rated Temperature
Range
• Triple Diode Protection on All Inputs
• Pin−for−Pin Compatible with CD4093
• Can be Used to Replace MC14011B
• Independent Schmitt−Trigger at each Input
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to V_SS)
Symbol
Parameter
Value
Unit
V_DD
V_in, V_out
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
−0.5 to +18.0
V
−0.5 to V_DD + 0.5
V
I_in, I_out Input or Output Current
(DC or Transient) per Pin
±10
mA
P_D Power Dissipation,
per Package (Note 1)
500
mW
T_A
Ambient Temperature Range
T_stg Storage Temperature Range
T_L
Lead Temperature
(8−Second Soldering)
−55 to +125
°C
−65 to +150
°C
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V_in and V_out should be constrained
to the range V_SS ≤ (V_in or V_out) ≤ V_DD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V_SS or V_DD). Unused outputs must be left open.
http://onsemi.com
SOIC−14
D SUFFIX
CASE 751A
SOEIAJ−14
F SUFFIX
CASE 965
TSSOP−14
DT SUFFIX
CASE 948G
PIN ASSIGNMENT
IN 1_A 1
IN 2_A 2
OUT_A 3
OUT_B 4
IN 1_B 5
IN 2_B 6
V_SS 7
14 V_DD
13 IN 2_D
12 IN 1_D
11 OUT_D
10 OUT_C
9 IN 2_C
8 IN 1C
MARKING DIAGRAMS
14
14
14093BG
AWLYWW
MC14093B
ALYWG
1
SOIC−14
1
SOEIAJ−14
14
14
093B
ALYW G
G
1
TSSOP−14
A
WL, L
YY, Y
WW, W
G or G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
1
August, 2014 − Rev. 10
Publication Order Number:
MC14093B/D