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MC14076B_05 Datasheet, PDF (1/8 Pages) ON Semiconductor – 4-Bit D-Type Register with Three-State Outputs | |||
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MC14076B
4âBit DâType Register
with ThreeâState Outputs
The MC14076B 4âBit Register consists of four Dâtype flipâflops
operating synchronously from a common clock. OR gated
outputâdisable inputs force the outputs into a highâimpedance state
for use in bus organized systems. OR gated dataâdisable inputs cause
the Q outputs to be fed back to the D inputs of the flipâflops. Thus they
are inhibited from changing state while the clocking process remains
undisturbed. An asynchronous master root is provided to clear all four
flipâflops simultaneously independent of the clock or disable inputs.
Features
⢠ThreeâState Outputs with Gated Control Lines
⢠Fully Independent Clock Allows Unrestricted Operation for the Two
Modes: Parallel Load and Do Nothing
⢠Asynchronous Master Reset
⢠Four Bus Buffer Registers
⢠Supply Voltage Range = 3.0 Vdc to 18 Vdc
⢠Capable of Driving Two LowâPower TTL Loads or One LowâPower
Schottky TTL Load Over the Rated Temperature Range
⢠PbâFree Packages are Available*
http://onsemi.com
MARKING
DIAGRAMS
PDIPâ16 16
P SUFFIX
CASE 648
1
MC14076BCP
AWLYYWW
SOICâ16
D SUFFIX
CASE 751B
16
14076B
AWLYWW
1
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
VDD
Vin, Vout
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
â0.5 to +18.0
V
â0.5 to VDD + 0.5
V
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
± 10
mA
PD
Power Dissipation, per Package
(Note 1)
500
mW
TA
Ambient Temperature Range
Tstg
Storage Temperature Range
TL
Lead Temperature
(8âSecond Soldering)
â55 to +125
°C
â65 to +150
°C
260
°C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Temperature Derating:
Plastic âP and D/DWâ Packages: â 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
highâimpedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
*For additional information on our PbâFree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
A
WL, L
YY, Y
WW, W
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
© Semiconductor Components Industries, LLC, 2005
1
February, 2005 â Rev. 5
Publication Order Number:
MC14076B/D
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