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MC14069UB_14 Datasheet, PDF (1/6 Pages) ON Semiconductor – Hex Inverter | |||
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MC14069UB
Hex Inverter
The MC14069UB hex inverter is constructed with MOS Pâchannel
and Nâchannel enhancement mode devices in a single monolithic
structure. These inverters find primary use where low power
dissipation and/or high noise immunity is desired. Each of the six
inverters is a single stage to minimize propagation delays.
Features
⢠Supply Voltage Range = 3.0 Vdc to 18 Vdc
⢠Capable of Driving Two LowâPower TTL Loads or One
LowâPower Schottky TTL Load Over the Rated Temperature
Range
⢠Triple Diode Protection on All Inputs
⢠PinâforâPin Replacement for CD4069UB
⢠Meets JEDEC UB Specifications
⢠NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AECâQ100
Qualified and PPAP Capable
⢠These Devices are PbâFree and are RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
VDD
Vin, Vout
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
â0.5 to +18.0
V
â0.5 to VDD + 0.5
V
Iin, Iout Input or Output Current
(DC or Transient) per Pin
±10
mA
PD Power Dissipation, per Package
(Note 1)
500
mW
TA
Ambient Temperature Range
Tstg Storage Temperature Range
â55 to +125
°C
â65 to +150
°C
TL
Lead Temperature
(8âSecond Soldering)
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: âD/DWâ Packages: â7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
highâimpedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS ⤠(Vin or Vout) ⤠VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
SOICâ14
D SUFFIX
CASE 751A
SOEIAJâ14
F SUFFIX
CASE 965
TSSOPâ14
DT SUFFIX
CASE 948G
PIN ASSIGNMENT
IN 1 1
OUT 1 2
IN 2 3
OUT 2 4
IN 3 5
OUT 3 6
VSS 7
14 VDD
13 IN 6
12 OUT 6
11 IN 5
10 OUT 5
9 IN 4
8 OUT 4
MARKING DIAGRAMS
14
14069UG
AWLYWW
1
SOICâ14
14
MC14069UB
ALYWG
1
SOEIAJâ14
14
14
069U
ALYWG
G
1
TSSOPâ14
A
WL, L
YY, Y
WW, W
G or G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= PbâFree Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
1
August, 2014 â Rev. 11
Publication Order Number:
MC14069UB/D
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