MC14069UB_06 Datasheet, PDF (1/7 Pages) ON Semiconductor – Hex Inverter

MC14069UB
Hex Inverter
The MC14069UB hex inverter is constructed with MOS P−channel
and N−channel enhancement mode devices in a single monolithic
structure. These inverters find primary use where low power
dissipation and/or high noise immunity is desired. Each of the six
inverters is a single stage to minimize propagation delays.
Features
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load Over the Rated Temperature Range
• Triple Diode Protection on All Inputs
• Pin−for−Pin Replacement for CD4069UB
• Meets JEDEC UB Specifications
• Pb−Free Packages are Available
MAXIMUM RATINGS (Voltages Referenced to V_SS)
Symbol
Parameter
Value
Unit
V_DD
V_in, V_out
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
−0.5 to +18.0
V
−0.5 to V_DD + 0.5
V
I_in, I_out Input or Output Current
(DC or Transient) per Pin
± 10
mA
P_D Power Dissipation, per Package
(Note 1)
500
mW
T_A
Ambient Temperature Range
T_stg Storage Temperature Range
T_L
Lead Temperature
(8−Second Soldering)
−55 to +125
°C
−65 to +150
°C
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V_in and V_out should be constrained
to the range V_SS v (V_in or V_out) v V_DD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V_SS or V_DD). Unused outputs must be left open.
http://onsemi.com
PDIP−14
P SUFFIX
CASE 646
MARKING
DIAGRAMS
14
MC14069UBCP
AWLYYWWG
1
14
SOIC−14
D SUFFIX
CASE 751A
14069UG
AWLYWW
1
TSSOP−14
DT SUFFIX
CASE 948G
14
14
069U
ALYWG
G
1
SOEIAJ−14
F SUFFIX
CASE 965
14
MC14069UB
ALYWG
1
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
G
© Semiconductor Components Industries, LLC, 2006
1
October, 2006 − Rev. 8
Publication Order Number:
MC14069UB/D