MC14049UB_04 Datasheet, PDF (1/8 Pages) ON Semiconductor – W Semiconductor Components Industries, LLC, 2004

MC14049UB
Hex Buffers
The MC14049UB hex inverter/buffer is constructed with MOS
P−channel and N−channel enhancement mode devices in a single
monolithic structure. This complementary MOS device finds primary
use where low power dissipation and/or high noise immunity is
desired. This device provides logic−level conversion using only one
supply voltage, V_DD. The input−signal high level (V_IH) can exceed the
V_DD supply voltage for logic−level conversions. Two TTL/DTL
Loads can be driven when the device is used as CMOS−to−TTL/DTL
converters (V_DD = 5.0 V, V_OL v 0.4 V, I_OL ≥ 3.2 mA). Note that pins
13 and 16 are not connected internally on this device; consequently
connections to these terminals will not affect circuit operation.
Features
• High Source and Sink Currents
• High−to−Low Level Converter
• Supply Voltage Range = 3.0 V to 18 V
• Meets JEDEC UB Specifications
• V_IN can exceed V_DD
• Improved ESD Protection on All Inputs
• Pb−Free Packages are Available*
MAXIMUM RATINGS (Voltages Referenced to V_SS)
Symbol
Parameter
Value
Unit
V_DD DC Supply Voltage Range
V_in
Input Voltage Range
(DC or Transient)
−0.5 to +18.0 V
−0.5 to +18.0 V
V_out Output Voltage Range
(DC or Transient)
−0.5 to V_DD
V
+0.5
I_in
Input Current
(DC or Transient) per Pin
± 10
mA
I_out
Output Current
(DC or Transient) per Pin
+45
mA
P_D
Power Dissipation, per Package (Note 1)
mW
Plastic
825
SOIC
740
T_A
Ambient Temperature Range
−55 to +125 °C
T_stg
Storage Temperature Range
−65 to +150 °C
T_L
Lead Temperature (8−Second Soldering)
260
°C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits
are exceeded, device functional operation is not implied, damage may occur
and reliability may be affected.
1. Temperature Derating: All Packages: See Figure 4.
This device contains circuitry to protect the inputs against damage due to high
static voltages or electric fields referenced to the V_SS pin, only. Extra precautions
must be taken to avoid applications of any voltage higher than the maximum rated
voltages to this high−impedance circuit. For proper operation, the ranges V_SS v
V_in v 18 V and V_SS v V_out v V_DD are recommended.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V_SS or V_DD). Unused outputs must be left open.
http://onsemi.com
PDIP−16
P SUFFIX
CASE 648
MARKING
DIAGRAMS
16
MC14049UBCP
AWLYYWW
1
SOIC−16
D SUFFIX
CASE 751B
16
14049U
AWLYWW
1
16
TSSOP−16
DT SUFFIX
CASE 948F
14
049U
ALYW
SOEIAJ−16
F SUFFIX
CASE 966
1
16
MC14049UB
ALYW
1
A
WL, L
YY, Y
WW, W
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
*For additional information on our Pb−Free strategy
and soldering details, please download the
ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2004
1
December, 2004 − Rev. 6
Publication Order Number:
MC14049UB/D