MC14049UB Datasheet, PDF (1/8 Pages) ON Semiconductor – Hex Buffers

MC14049UB
Hex Buffers
The MC14049UB hex inverter/buffer is constructed with MOS
P–channel and N–channel enhancement mode devices in a single
monolithic structure. This complementary MOS device finds primary
use where low power dissipation and/or high noise immunity is
desired. This device provides logic–level conversion using only one
supply voltage, V_DD. The input–signal high level (V_IH) can exceed the
V_DD supply voltage for logic–level conversions. Two TTL/DTL
v ^{Loads can be driven when the device is used as CMOS–to–TTL/DTL}
converters (V_DD = 5.0 V, V_OL 0.4 V, I_OL ≥ 3.2 mA). Note that pins
13 and 16 are not connected internally on this device; consequently
connections to these terminals will not affect circuit operation.
• High Source and Sink Currents
• High–to–Low Level Converter
• Supply Voltage Range = 3.0 V to 18 V
• Meets JEDEC UB Specifications
• V_IN can exceed V_DD
• Improved ESD Protection on All Inputs
MAXIMUM RATINGS (Voltages Referenced to V_SS) (Note 2.)
Symbol
Parameter
Value
Unit
V_DD
DC Supply Voltage Range
V_in
Input Voltage Range
(DC or Transient)
– 0.5 to +18.0
V
– 0.5 to +18.0
V
V_out
Output Voltage Range
(DC or Transient)
– 0.5 to V_DD +0.5
V
I_in
Input Current
(DC or Transient) per Pin
± 10
mA
I_out
Output Current
(DC or Transient) per Pin
+45
mA
P_D
Power Dissipation,
per Package (Note 3.)
Plastic
SOIC
mW
825
740
T_A
Ambient Temperature Range
T_stg
Storage Temperature Range
T_L
Lead Temperature
(8–Second Soldering)
– 55 to +125
°C
– 65 to +150
°C
260
°C
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
All Packages: See Figure 4.
This device contains circuitry to protect the inputs against damage due to high
static voltages or electric fields referenced to the V_SS pin, only. Extra precautions
must be taken to avoid applications of any voltage higher than the maximum rated
v voltages to this high–impedance circuit. For proper operation, the ranges V_SS
v v v V_in 18 V and V_SS V_out V_DD are recommended.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V_SS or V_DD). Unused outputs must be left open.
© Semiconductor Components Industries, LLC, 2000
1
March, 2000 – Rev. 3
http://onsemi.com
PDIP–16
P SUFFIX
CASE 648
MARKING
DIAGRAMS
16
MC14049UBCP
AWLYYWW
1
SOIC–16
D SUFFIX
CASE 751B
16
14049U
AWLYWW
1
16
TSSOP–16
DT SUFFIX
CASE 948F
14
049U
ALYW
SOEIAJ–16
F SUFFIX
CASE 966
1
16
MC14049U
AWLYWW
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC14049UBCP PDIP–16
2000/Box
MC14049UBD
SOIC–16
2400/Box
MC14049UBDR2 SOIC–16 2500/Tape & Reel
MC14049UBDT TSSOP–16
96/Rail
MC14049UBDTR2 TSSOP–16 2500/Tape & Reel
MC14049UBF SOEIAJ–16 See Note 1.
MC14049UBFEL SOEIAJ–16 See Note 1.
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
Publication Order Number:
MC14049UB/D