MC14049B Datasheet, PDF (1/8 Pages) ON Semiconductor – Hex Buffer

MC14049B, MC14050B
Hex Buffer
The MC14049B Hex Inverter/Buffer and MC14050B Noninverting
Hex Buffer are constructed with MOS P−Channel and N−Channel
enhancement mode devices in a single monolithic structure. These
complementary MOS devices find primary use where low power
dissipation and/or high noise immunity is desired. These devices
provide logic level conversion using only one supply voltage, V_DD.
The input−signal high level (V_IH) can exceed the V_DD supply
voltage for logic level conversions. Two TTL/DTL loads can be driven
when the devices are used as a CMOS−to−TTL/DTL converter
(V_DD = 5.0 V, V_OL v 0.4 V, I_OL ≥ 3.2 mA).
Note that pins 13 and 16 are not connected internally on these
devices; consequently connections to these terminals will not affect
circuit operation.
Features
• High Source and Sink Currents
• High−to−Low Level Converter
• Supply Voltage Range = 3.0 V to 18 V
• V_IN can exceed V_DD
• Meets JEDEC B Specifications
• Improved ESD Protection On All Inputs
• Pb−Free Packages are Available*
MAXIMUM RATINGS (Voltages Referenced to V_SS)
Symbol
Parameter
Value
Unit
V_DD DC Supply Voltage Range
−0.5 to +18.0 V
V_in Input Voltage Range (DC or Transient) −0.5 to +18.0 V
V_out Output Voltage Range (DC or Transient) −0.5 to V_DD + V
0.5
I_in
Input Current (DC or Transient) per Pin
± 10
mA
I_out Output Current (DC or Transient) per Pin
± 45
mA
P_D Power Dissipation, per Package (Note 1)
mW
(Plastic)
825
(SOIC)
740
T_A
Ambient Temperature Range
−55 to +125 °C
T_stg Storage Temperature Range
−65 to +150 °C
T_L
Lead Temperature (8−Second Soldering)
260
°C
1. Temperature Derating: See Figure 3.
This device contains protection circuitry to protect the inputs against damage
due to high static voltages or electric fields referenced to the V_SS pin only. Extra
precautions must be taken to avoid applications of any voltage higher than the
maximum rated voltages to this high−impedance circuit. For proper operation, the
ranges V_SS ≤ V_in ≤ 18 V and V_SS ≤ V_out ≤ V_DD are recommended.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V_SS or V_DD). Unused outputs must be left open.
http://onsemi.com
MARKING
DIAGRAMS
PDIP−16 ¹⁶
P SUFFIX
CASE 648
1
MC140xxBCP
AWLYYWW
SOIC−16
D SUFFIX
CASE 751B
16
140xxB
AWLYWW
1
TSSOP−16
DT SUFFIX
CASE 948F
16
14
0xxB
ALYW
1
SOEIAJ−16
F SUFFIX
CASE 966
16
MC140xxB
AWLYWW
1
xx
A
WL, L
YY, Y
WW, W
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2005
1
February, 2005 − Rev. 5
Publication Order Number:
MC14049B/D