MC14043B_14 Datasheet, PDF (1/7 Pages) ON Semiconductor – CMOS MSI Quad R−S Latches

MC14043B, MC14044B
CMOS MSI
Quad R−S Latches
The MC14043B and MC14044B quad R−S latches are constructed
with MOS P−Channel and N−Channel enhancement mode devices in
a single monolithic structure. Each latch has an independent Q output
and set and reset inputs. The Q outputs are gated through three−state
buffers having a common enable input. The outputs are enabled with
a logical “1” or high on the enable input; a logical “0” or low
disconnects the latch from the Q outputs, resulting in an open circuit at
the Q outputs.
Features
• Double Diode Input Protection
• Three−State Outputs with Common Enable
• Outputs Capable of Driving Two Low−power TTL Loads or One
Low−Power Schottky TTL Load Over the Rated Temperature
Range
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to V_SS)
Symbol
Parameter
Value
Unit
V_DD
V_in, V_out
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
−0.5 to +18.0
V
−0.5 to V_DD + 0.5
V
I_in, I_out
Input or Output Current
(DC or Transient) per Pin
± 10
mA
P_D
Power Dissipation, per Package
(Note 1)
500
mW
T_A
Ambient Temperature Range
T_stg
Storage Temperature Range
T_L
Lead Temperature
(8−Second Soldering)
−55 to +125
°C
−65 to +150
°C
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V_in and V_out should be constrained
to the range V_SS ≤ (V_in or V_out) ≤ V_DD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V_SS or V_DD). Unused outputs must be left open.
http://onsemi.com
SOIC−16
D SUFFIX
CASE 751B
SOEIAJ−16
F SUFFIX
CASE 966
MARKING DIAGRAMS
16
140xxBG
AWLYWW
1
SOIC−16
16
MC14043B
ALYWG
1
SOEIAJ−16
xx
A
WL, L
YY, Y
WW, W
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Indicator
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
1
August, 2014 − Rev. 10
Publication Order Number:
MC14043B/D