MC14042B_14 Datasheet, PDF (1/6 Pages) ON Semiconductor – Quad Transparent Latch

MC14042B
Quad Transparent Latch
The MC14042B Quad Transparent Latch is constructed with MOS
P−channel and N−channel enhancement mode devices in a single
monolithic structure. Each latch has a separate data input, but all four
latches share a common clock. The clock polarity (high or low) used to
strobe data through the latches can be reversed using the polarity
input. Information present at the data input is transferred to outputs Q
and Q during the clock level which is determined by the polarity input.
When the polarity input is in the logic “0” state, data is transferred
during the low clock level, and when the polarity input is in the logic
“1” state the transfer occurs during the high clock level.
Features
• Buffered Data Inputs
• Common Clock
• Clock Polarity Control
• Q and Q Outputs
• Double Diode Input Protection
• Supply Voltage Range = 3.0 Vdc to 1 8 Vdc
• Capable of Driving Two Low−power TTL Loads or One Low−power
Schottky TTL Load Over the Rated Temperature Range
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• This Device is Pb−Free and is RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to V_SS)
Symbol
Parameter
Value
Unit
V_DD
DC Supply Voltage Range
−0.5 to +18.0
V
V_in, V_out Input or Output Voltage Range −0.5 to V_DD + 0.5
V
(DC or Transient)
I_in, I_out
Input or Output Current
(DC or Transient) per Pin
±10
mA
P_D
Power Dissipation,
per Package (Note 1)
500
mW
T_A
Ambient Temperature Range
T_stg
Storage Temperature Range
T_L
Lead Temperature
(8−Second Soldering)
−55 to +125
°C
−65 to +150
°C
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V_in and V_out should be constrained
to the range V_SS ≤ (V_in or V_out) ≤ V_DD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V_SS or V_DD). Unused outputs must be left open.
http://onsemi.com
SOIC−16
D SUFFIX
CASE 751B
PIN ASSIGNMENT
Q3 1
Q0 2
Q0 3
D0 4
CLOCK 5
POLARITY 6
D1 7
V_SS 8
16 V_DD
15 Q3
14 D3
13 D2
12 Q2
11 Q2
10 Q1
9 Q1
MARKING DIAGRAM
16
14042BG
AWLYWW
1
A
WL
YY, Y
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Indicator
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
1
August, 2014 − Rev. 9
Publication Order Number:
MC14042B/D