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MC14042B Datasheet, PDF (1/8 Pages) ON Semiconductor – Quad Transparent Latch | |||
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MC14042B
Quad Transparent Latch
The MC14042B Quad Transparent Latch is constructed with MOS
Pâchannel and Nâchannel enhancement mode devices in a single
monolithic structure. Each latch has a separate data input, but all four
latches share a common clock. The clock polarity (high or low) used to
strobe data through the latches can be reversed using the polarity
input. Information present at the data input is transferred to outputs Q
and Q during the clock level which is determined by the polarity input.
When the polarity input is in the logic â0â state, data is transferred
during the low clock level, and when the polarity input is in the logic
â1â state the transfer occurs during the high clock level.
⢠Buffered Data Inputs
⢠Common Clock
⢠Clock Polarity Control
⢠Q and Q Outputs
⢠Double Diode Input Protection
⢠Supply Voltage Range = 3.0 Vdc to 1 8 Vdc
⢠Capable of Driving Two Lowâpower TTL Loads or One Lowâpower
Schottky TTL Load Over the Rated Temperature Range
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
Symbol
Parameter
Value
Unit
VDD
DC Supply Voltage Range
â 0.5 to +18.0
V
Vin, Vout Input or Output Voltage Range â 0.5 to VDD + 0.5
V
(DC or Transient)
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
± 10
mA
PD
Power Dissipation,
per Package (Note 3.)
500
mW
TA
Ambient Temperature Range
Tstg
Storage Temperature Range
TL
Lead Temperature
(8âSecond Soldering)
â 55 to +125
°C
â 65 to +150
°C
260
°C
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic âP and D/DWâ Packages: â 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
v v highâimpedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
PDIPâ16
P SUFFIX
CASE 648
MARKING
DIAGRAMS
16
MC14042BCP
AWLYYWW
1
SOICâ16
D SUFFIX
CASE 751B
16
14042B
AWLYWW
1
SOEIAJâ16
F SUFFIX
CASE 966
16
MC14042B
AWLYWW
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC14042BCP
PDIPâ16
2000/Box
MC14042BD
SOICâ16
2400/Box
MC14042BDR2 SOICâ16 2500/Tape & Reel
MC14042BF
SOEIAJâ16 See Note 1.
MC14042BFEL SOEIAJâ16 See Note 1.
MC14042BFR1 SOEIAJâ16 See Note 1.
MC14042BFR2 SOEIAJâ16 See Note 1.
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
© Semiconductor Components Industries, LLC, 2000
1
March, 2000 â Rev. 3
Publication Order Number:
MC14042B/D
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