MC14028B_14 Datasheet, PDF (1/6 Pages) ON Semiconductor – BCD-To-Decimal Decoder Binary-To-Octal Decoder

MC14028B
BCD-To-Decimal Decoder
Binary-To-Octal Decoder
The MC14028B decoder is constructed so that an 8421 BCD code
on the four inputs provides a decimal (one−of−ten) decoded output,
while a 3−bit binary input provides a decoded octal (one−of−eight)
code output with D forced to a logic “0”. Expanded decoding such as
binary−to−hexadecimal (one−of−sixteen), etc., can be achieved by
using other MC14028B devices. The part is useful for code
conversion, address decoding, memory selection control,
demultiplexing, or readout decoding.
Features
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low−power TTL Loads or One Low−Power
Schottky TTL Load Over the Rated Temperature Range
• Positive Logic Design
• Low Outputs on All Illegal Input Combinations
• Similar to CD4028B
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• This Device is Pb−Free and is RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to V_SS)
Parameter
Symbol
Value
Unit
DC Supply Voltage Range
V_DD −0.5 to +18.0 V
Input or Output Voltage Range
(DC or Transient)
V_in, V_out − 0.5 to V_DD
V
+ 0.5
Input or Output Current (DC or Transient) I_in, I_out
± 10
mA
per Pin
Power Dissipation per Package (Note 1)
P_D
500
mW
Ambient Temperature Range
T_A
−55 to +125 °C
Storage Temperature Range
T_stg
−65 to +150 °C
Lead Temperature (8−Second Soldering)
T_L
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V_in and V_out should be constrained
to the range V_SS ≤ (V_in or V_out) ≤ V_DD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V_SS or V_DD). Unused outputs must be left open.
http://onsemi.com
SOIC−16
D SUFFIX
CASE 751B
PIN ASSIGNMENT
Q4 1
Q2 2
Q0 3
Q7 4
Q9 5
Q5 6
Q6 7
V_SS 8
16 V_DD
15 Q3
14 Q1
13 B
12 C
11 D
10 A
9 Q8
MARKING DIAGRAM
16
14028BG
AWLYWW
1
A
WL
YY, Y
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
1
August, 2014 − Rev. 9
Publication Order Number:
MC14028B/D