MC14027B_14 Datasheet, PDF (1/6 Pages) ON Semiconductor – Dual J-K Flip-Flop

MC14027B
Dual J-K Flip-Flop
The MC14027B dual J−K flip−flop has independent J, K, Clock (C),
Set (S) and Reset (R) inputs for each flip−flop. These devices may be
used in control, register, or toggle functions.
Features
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Logic Swing Independent of Fanout
• Logic Edge−Clocked Flip−Flop Design
• Logic State is Retained Indefinitely with Clock Level Either High or
Low; Information is Transferred to the Output Only on the
Positive−Going Edge of the Clock Pulse
• Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load Over the Rated Temperature Range
• Pin−for−Pin Replacement for CD4027B
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• This Device is Pb−Free and is RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to V_SS)
Symbol
Parameter
Value
Unit
V_DD
DC Supply Voltage Range
−0.5 to +18.0
V
V_in, V_out Input or Output Voltage Range −0.5 to V_DD + 0.5
V
(DC or Transient)
I_in, I_out
Input or Output Current
(DC or Transient) per Pin
± 10
mA
P_D
Power Dissipation, per Package
500
mW
(Note 1)
T_A
Ambient Temperature Range
−55 to +125
°C
T_stg
Storage Temperature Range
−65 to +150
°C
T_L
Lead Temperature
(8−Second Soldering)
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V_in and V_out should be constrained
to the range V_SS ≤ (V_in or V_out) ≤ V_DD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V_SS or V_DD). Unused outputs must be left open.
http://onsemi.com
SOIC−16
D SUFFIX
CASE 751B
PIN ASSIGNMENT
Q_A 1
Q_A 2
C_A 3
R_A 4
K_A 5
J_A 6
S_A 7
V_SS 8
16 V_DD
15 Q_B
14 Q_B
13 C_B
12 R_B
11 K_B
10 J_B
9 S_B
MARKING DIAGRAM
16
14027BG
AWLYWW
1
A
WL
YY, Y
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Indicator
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
1
August, 2014 − Rev. 8
Publication Order Number:
MC14027B/D