MC14027B_05 Datasheet, PDF (1/8 Pages) ON Semiconductor – Dual J−K Flip−Flop

MC14027B
Dual J−K Flip−Flop
The MC14027B dual J−K flip−flop has independent J, K, Clock (C),
Set (S) and Reset (R) inputs for each flip−flop. These devices may be
used in control, register, or toggle functions.
Features
• Diode Protection on All Inputs
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Logic Swing Independent of Fanout
• Logic Edge−Clocked Flip−Flop Design
• Logic State is Retained Indefinitely with Clock Level Either High or
Low; Information is Transferred to the Output Only on the
Positive−Going Edge of the Clock Pulse
• Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load Over the Rated Temperature Range
• Pin−for−Pin Replacement for CD4027B
• Pb−Free Packages are Available*
MAXIMUM RATINGS (Voltages Referenced to V_SS)
Symbol
Parameter
Value
Unit
V_DD
DC Supply Voltage Range
−0.5 to +18.0
V
V_in, V_out Input or Output Voltage Range −0.5 to V_DD + 0.5
V
(DC or Transient)
I_in, I_out
Input or Output Current
(DC or Transient) per Pin
± 10
mA
P_D
Power Dissipation, per Package
500
mW
(Note 1)
T_A
Ambient Temperature Range
T_stg
Storage Temperature Range
T_L
Lead Temperature
(8−Second Soldering)
−55 to +125
°C
−65 to +150
°C
260
°C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
http://onsemi.com
MARKING
DIAGRAMS
PDIP−16 ¹⁶
P SUFFIX
CASE 648
1
MC14027BCP
AWLYYWWG
SOIC−16
D SUFFIX
CASE 751B
16
14027BG
AWLYWW
1
SOEIAJ−16
F SUFFIX
CASE 966
16
MC14027B
ALYWG
1
A
WL, L
YY, Y
WW, W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Indicator
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V_in and V_out should be constrained
to the range V_SS v (V_in or V_out) v V_DD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V_SS or V_DD). Unused outputs must be left open.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2005
1
August, 2005 − Rev. 6
Publication Order Number:
MC14027B/D