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MC14020B_14 Datasheet, PDF (1/7 Pages) ON Semiconductor – 14-Bit Binary Counter | |||
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MC14020B
14-Bit Binary Counter
The MC14020B 14âstage binary counter is constructed with MOS
PâChannel and NâChannel enhancement mode devices in a single
monolithic structure. This part is designed with an input wave shaping
circuit and 14 stages of rippleâcarry binary counter. The device
advances the count on the negativeâgoing edge of the clock pulse.
Applications include time delay circuits, counter controls, and
frequencyâdividing circuits.
Features
⢠Fully Static Operation
⢠Diode Protection on All Inputs
⢠Supply Voltage Range = 3.0 Vdc to 18 Vdc
⢠Capable of Driving Two Lowâpower TTL Loads or One Lowâpower
Schottky TTL Load Over the Rated Temperature Range
⢠Buffered Outputs Available from stages 1 and 4 thru 14
⢠Common Reset Line
⢠PinâforâPin Replacement for CD4020B
⢠NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AECâQ100
Qualified and PPAP Capable
⢠These Devices are PbâFree and are RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
VDD
Vin, Vout
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
â0.5 to +18.0
V
â0.5 to VDD + 0.5
V
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
±10
mA
PD
Power Dissipation, per Package
(Note 1)
500
mW
TA
Ambient Temperature Range
Tstg
Storage Temperature Range
TL
Lead Temperature
(8âSecond Soldering)
â55 to +125
°C
â65 to +150
°C
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: âD/DWâ Packages: â7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
highâimpedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS ⤠(Vin or Vout) ⤠VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
SOICâ16
D SUFFIX
CASE 751B
TSSOPâ16
DT SUFFIX
CASE 948F
PIN ASSIGNMENT
Q12 1
Q13 2
Q14 3
Q6 4
Q5 5
Q7 6
Q4 7
VSS 8
16 VDD
15 Q11
14 Q10
13 Q8
12 Q9
11 R
10 C
9 Q1
MARKING DIAGRAMS
16
14020BG
AWLYWW
1
SOICâ16
16
14
020B
ALYWG
G
1
TSSOPâ16
A
WL, L
YY, Y
WW, W
G or G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= PbâFree Indicator
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
1
August, 2014 â Rev. 9
Publication Order Number:
MC14020B/D
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