MC14012B_06 Datasheet, PDF (1/9 Pages) ON Semiconductor – B−Suffix Series CMOS Gates

MC14012B
B−Suffix Series CMOS Gates
The B Series logic gates are constructed with P−Channel and
N−Channel enhancement mode devices in a single monolithic
structure (Complementary MOS). Their primary use is where low
power dissipation and/or high noise immunity is desired.
Features
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• All Outputs Buffered
• Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load Over the Rated Temperature Range
• Double Diode Protection on All Inputs
• Pin−for−Pin Replacements for Corresponding CD4000 Series B
Suffix Devices
• Pb−Free Packages are Available
MAXIMUM RATINGS (Voltages Referenced to V_SS)
Symbol
Parameter
Value
Unit
V_DD
V_in, V_out
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
−0.5 to +18.0
V
−0.5 to V_DD + 0.5
V
I_in, I_out
Input or Output Current
(DC or Transient) per Pin
± 10
mA
P_D
Power Dissipation, per Package
500
mW
(Note 1)
T_A
Ambient Temperature Range
−55 to +125
°C
T_stg
Storage Temperature Range
−65 to +150
°C
T_L
Lead Temperature
(8−Second Soldering)
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V_in and V_out should be constrained
to the range V_SS v (V_in or V_out) v V_DD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V_SS or V_DD). Unused outputs must be left open.
http://onsemi.com
MARKING
DIAGRAMS
PDIP−14
P SUFFIX
CASE 646
14
MC14012BCP
AWLYYWWG
1
14
SOIC−14
D SUFFIX
CASE 751A
14012BG
AWLYWW
1
SOEIAJ−14
F SUFFIX
CASE 965
14
MC14012B
ALYWG
1
A
WL, L
YY, Y
WW, W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
1
October, 2006 − Rev. 7
Publication Order Number:
MC14012B/D