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MC14001UB_09 Datasheet, PDF (1/7 Pages) ON Semiconductor – UB-Suffix Series CMOS Gates | |||
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MC14001UB, MC14011UB
UB-Suffix Series
CMOS Gates
The UB Series logic gates are constructed with P and N channel
enhancement mode devices in a single monolithic structure
(Complementary MOS). Their primary use is where low power
dissipation and/or high noise immunity is desired. The UB set of
CMOS gates are inverting nonâbuffered functions.
Features
⢠Supply Voltage Range = 3.0 Vdc to 18 Vdc
⢠Linear and Oscillator Applications
⢠Capable of Driving Two LowâPower TTL Loads or One
LowâPower Schottky TTL Load Over the Rated Temperature Range
⢠Double Diode Protection on All Inputs
⢠PinâforâPin Replacements for Corresponding CD4000 Series UB
Suffix Devices
⢠These are PbâFree Devices
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
VDD
Vin, Vout
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
â0.5 to +18.0
V
â0.5 to VDD + 0.5
V
Iin, Iout
Input or Output Current
(DC or Transient) per Pin
± 10
mA
PD
Power Dissipation, per Package
(Note 1)
500
mW
TA
Ambient Temperature Range
â55 to +125
°C
Tstg
Storage Temperature Range
â65 to +150
°C
TL
Lead Temperature
(8âSecond Soldering)
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
Plastic âP and D/DWâ Packages: â 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
highâimpedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
MARKING
DIAGRAMS
14
PDIPâ14
P SUFFIX
CASE 646
MC140xxUBCP
AWLYYWWG
1
14
SOICâ14
D SUFFIX
CASE 751A
140xxUG
AWLYWW
1
xx
A
WL, L
YY, Y
WW, W
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= PbâFree Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
© Semiconductor Components Industries, LLC, 2009
1
September, 2009 â Rev. 7
Publication Order Number:
MC14001UB/D
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