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MC14001B_14 Datasheet, PDF (1/11 Pages) ON Semiconductor – B-Suffix Series CMOS Gates | |||
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MC14001B Series
B-Suffix Series CMOS Gates
MC14001B, MC14011B, MC14023B,
MC14025B, MC14071B, MC14073B,
MC14081B, MC14082B
The B Series logic gates are constructed with P and N channel
enhancement mode devices in a single monolithic structure
(Complementary MOS). Their primary use is where low power
dissipation and/or high noise immunity is desired.
Features
⢠Supply Voltage Range = 3.0 Vdc to 18 Vdc
⢠All Outputs Buffered
⢠Capable of Driving Two Lowâpower TTL Loads or One Lowâpower
Schottky TTL Load Over the Rated Temperature Range.
⢠Double Diode Protection on All Inputs Except: Triple Diode
Protection on MC14011B and MC14081B
⢠PinâforâPin Replacements for Corresponding CD4000 Series
B Suffix Devices
⢠NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AECâQ100
Qualified and PPAP Capable
⢠These Devices are PbâFree and are RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
VDD
Vin, Vout
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
â0.5 to +18.0
V
â0.5 to VDD + 0.5 V
Iin, Iout Input or Output Current
(DC or Transient) per Pin
± 10
mA
PD Power Dissipation, per Package
(Note 1)
500
mW
TA
Ambient Temperature Range
Tstg Storage Temperature Range
TL
Lead Temperature
(8âSecond Soldering)
â55 to +125
°C
â65 to +150
°C
260
°C
VESD ESD Withstand Voltage
V
Human Body Model
> 3000
Machine Model
> 300
Charged Device Model
N/A
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: âD/DWâ Packages: â7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
highâimpedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS ⤠(Vin or Vout) ⤠VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
SOICâ14
D SUFFIX
CASE 751A
TSSOPâ14
DT SUFFIX
CASE 948G
MARKING DIAGRAMS
14
140xxBG
AWLYWW
1
SOICâ14
14
14
0xxB
ALYWG
G
1
TSSOPâ14
xx
A
WL, L
YY, Y
WW, W
G or G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= PbâFree Package
(Note: Microdot may be in either location)
DEVICE INFORMATION
Device
MC14001B
MC14011B
MC14023B
Description
Quad 2âInput NOR Gate
Quad 2âInput NAND Gate
Triple 3âInput NAND Gate
MC14025B
MC14071B
MC14073B
Triple 3âInput NOR Gate
Quad 2âInput OR Gate
Triple 3âInput AND Gate
MC14081B
MC14082B
Quad 2âInput AND Gate
Dual 4âInput AND Gate
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
1
July, 2014 â Rev. 11
Publication Order Number:
MC14001B/D
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