MC14001B Datasheet, PDF (1/12 Pages) ON Semiconductor – B-Suffix Series CMOS Gates

MC14001B Series
B−Suffix Series CMOS Gates
MC14001B, MC14011B, MC14023B,
MC14025B, MC14071B, MC14073B,
MC14081B, MC14082B
The B Series logic gates are constructed with P and N channel
enhancement mode devices in a single monolithic structure
(Complementary MOS). Their primary use is where low power
dissipation and/or high noise immunity is desired.
Features
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• All Outputs Buffered
• Capable of Driving Two Low−power TTL Loads or One Low−power
Schottky TTL Load Over the Rated Temperature Range.
• Double Diode Protection on All Inputs Except: Triple Diode
Protection on MC14011B and MC14081B
• Pin−for−Pin Replacements for Corresponding CD4000 Series
B Suffix Devices
• Pb−Free Packages are Available*
MAXIMUM RATINGS (Voltages Referenced to V_SS)
Symbol
Parameter
Value
Unit
V_DD
V_in, V_out
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
−0.5 to +18.0
V
−0.5 to V_DD + 0.5 V
I_in, I_out Input or Output Current
(DC or Transient) per Pin
± 10
mA
P_D Power Dissipation, per Package
(Note 1)
500
mW
T_A
Ambient Temperature Range
−55 to +125
°C
T_stg Storage Temperature Range
−65 to +150
°C
T_L
Lead Temperature
(8−Second Soldering)
260
°C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V_in and V_out should be constrained
to the range V_SS v (V_in or V_out) v V_DD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V_SS or V_DD). Unused outputs must be left open.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
http://onsemi.com
MARKING
DIAGRAMS
PDIP−14
P SUFFIX
CASE 646
14
MC140xxBCP
AWLYYWW
1
14
SOIC−14
D SUFFIX
CASE 751A
140xxB
AWLYWW
1
14
TSSOP−14
DT SUFFIX
CASE 948G
14
0xxB
ALYW
SOEIAJ−14
F SUFFIX
CASE 965
1
14
MC140xxB
AWLYWW
1
xx
A
WL, L
YY, Y
WW, W
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
DEVICE INFORMATION
Device
MC14001B
MC14011B
MC14023B
Description
Quad 2−Input NOR Gate
Quad 2−Input NAND Gate
Triple 3−Input NAND Gate
MC14025B
MC14071B
MC14073B
Triple 3−Input NOR Gate
Quad 2−Input OR Gate
Triple 3−Input AND Gate
MC14081B
MC14082B
Quad 2−Input AND Gate
Dual 4−Input AND Gate
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
© Semiconductor Components Industries, LLC, 2005
1
February, 2005 − Rev. 4
Publication Order Number:
MC14001B/D