MC10H603 Datasheet, PDF (1/5 Pages) ON Semiconductor – 9-Bit Latch ECL/TTL Translator

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
9-Bit Latch ECLā/āTTL
Translator
The MC10H/100H603 is a 9–bit, dual supply ECL to TTL translator.
Devices in the Motorola 9–bit translator series utilize the 28–lead PLCC for
optimal power pinning, signal flow–through and electrical performance.
The devices feature a 48 mA TTL output stage, and AC performance is
specified into both a 50 pF and 200 pF load capacitance. Latching is
controlled by Latch Enable (LEN), and Master Reset (MR) resets the
latches. A HIGH on OEECL sends the outputs into the high impedance
state. All control inputs are ECL level.
The 10H version is compatible with MECL 10H ECL logic levels. The
100H version is compatible with 100K levels.
• 9–Bit Ideal for Byte–Parity Applications
• 3–State TTL Outputs
• Flow–Through Configuration
• Extra TTL and ECL Power Pins to Minimize Switching Noise
• Dual Supply
• 6.0 ns Max Delay into 50 pF, 12 ns into 200 pF (all outputs switching)
• PNP TTL Inputs for Low Loading
OEECL
D0
D1
D2
D3
ECL _D4
D5
D6
D7
D8
LEN
MR
LOGIC SYMBOL
DQ
Q0
EN
DQ
Q1
EN
DQ
Q2
EN
DQ
Q3
EN
DQ
Q4
TTL
EN
DQ
Q5
EN
DQ
Q6
EN
DQ
Q7
EN
DQ
Q8
EN
MC10H603
MC100H603
FN SUFFIX
PLASTIC PACKAGE
CASE 776–02
PIN NAMES
PIN
FUNCTION
GND
VCCE
VCCT
VEE
D0 – D8
Q0 – Q8
OEECL
LEN
MR
TTL Ground (0 V)
ECL VCC (0 V)
TTL Supply (+ 5.0 V)
ECL Supply (– 5.2 / – 4.5 V)
Data Inputs (ECL)
Data Outputs (TTL)
3-State Control (ECL)
Latch Enable (ECL)
Master Reset (ECL)
TRUTH TABLE
D LEN MR OEECL
Q
L
L
L
L
L
H
L
L
L
H
X
H
L
L
Q0
X
X
H
L
L
X
X
X
H
Z
Pinout: 28–Lead PLCC (Top View)
Q5 GND VCCT Q6 GND Q7 Q8
25 24 23 22 21 20 19
Q4 26
18 D8
Q3 27
17 _D7
VCCT 28
Q2
16 _VCCE
15 D6
GND 2
14 D5
Q1 3
13 D4
Q0 4
12 D3
5
6
7
8
9 10 11
MR LEN OEECL VEE D0 D1 D2
3/93
© Motorola, Inc. 1996
2–311
REV 5