MC10H602 Datasheet, PDF (1/4 Pages) ON Semiconductor – 9-Bit Latch TTL/ECL Translator

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
9-Bit Latch TTLā/āECL
Translator
The MC10H/100H602 is a 9–bit, dual supply TTL to ECL translator with
latch. Devices in the Motorola 9–bit translator series utilize the 28–lead
PLCC for optimal power pinning, signal flow–through and electrical
performance.
The H602 features D–type latches. Latching is controlled by Latch
Enable (LEN), while the Master Reset input resets the latches. A
post–latch logic enable is also provided (ENECL), allowing control of the
output state without destroying latch data. All control inputs are ECL level.
The 10H version is compatible with MECL 10H ECL logic levels. The
100H version is compatible with 100K levels.
• 9–Bit Ideal for Byte–Parity Applications
• Flow–Through Configuration
• Extra TTL and ECL Power/Ground Pins to Minimize Switching Noise
• Dual Supply
• 3.5 ns Max D to Q
• PNP TTL Inputs for Low Loading
LOGIC SYMBOL
ENECL
D0
DQ
EN
D1
DQ
EN
D2
DQ
EN
D3
DQ
EN
TTL
D4
DQ
EN
D5
DQ
EN
D6
DQ
EN
D7
DQ
EN
D8
DQ
EN
LEN
MR
Q0
Q1
Q2
Q3
Q4 ECL
Q5
Q6
Q7
Q8
MC10H602
MC100H602
FN SUFFIX
PLASTIC PACKAGE
CASE 776–02
PIN NAMES
PIN
FUNCTION
GND
VCCE
VCCO
VCCT
VEE
D0 – D8
Q0 – Q8
ENECL
LEN
MR
TTL Ground (0 V)
ECL VCC (0 V)
ECL VCC (0 V) — Outputs
TTL Supply (+ 5.0 V)
ECL Supply (– 5.2 / – 4.5 V)
Data Inputs (TTL)
Data Outputs (ECL)
Enable Control (ECL)
Latch Enable (ECL)
Master Reset (ECL)
TRUTH TABLE
D LEN MR ENECL
Q
L
L
L
H
L
H
L
L
H
H
X
H
L
H
Q0
X
X
H
H
L
X
X
X
L
L
Pinout: 28–Lead PLCC (Top View)
D5 D4 VCCT D3 D2 D1 D0
25 24 23 22 21 20 19
D6 26
18 Q0
D7 27
17 _Q1
D8 28
GND
MR 2
16 _VCCE
15 VCCO
14 Q2
LEN 3
13 VCCO
ENECL 4
12 Q3
5 6 7 8 9 10 11
Q8 Q7 VCCO Q6 VEE Q5 Q4
3/93
© Motorola, Inc. 1996
2–307
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